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公开(公告)号：US09362924B1
公开(公告)日：2016-06-07
申请号：US14794770
申请日：2015-07-08
Applicant: Integrated Device Technology, Inc.
Inventor： Changxi Xu , Hui Li
CPC classification number: H03L7/085 , G04F10/005 , H03J2200/10 , H03J2200/15 , H03L7/0992 , H03L7/10
Abstract: A Method and Apparatus for Fast Frequency Acquisition in PLL System has been disclosed. In one implementation a time to digital converter is used with cycle slip detection for fast acquisition and lock. In one implementation cycle slip detection is applied to determine if a feedback clock from an oscillator is faster than a reference clock or not in one measurement cycle.
Abstract translation: 已经公开了用于PLL系统中的快速频率采集的方法和装置。 在一个实现中，使用数字转换器的循环滑移检测用于快速采集和锁定。 在一个实现周期中，应用滑动检测来确定来自振荡器的反馈时钟是否比一个测量周期中的参考时钟快。
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公开(公告)号：US20190028105A1
公开(公告)日：2019-01-24
申请号：US16139340
申请日：2018-09-24
Applicant: Integrated Device Technology, Inc.
Inventor： Hui Li , Teck-Chuan Ng , Stephen E. Aycock
Abstract: An apparatus includes a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate a first code by counting a number of cycles of an input clock signal during a period. The period may be determined by an output clock signal and a second code. The second circuit may be configured to generate a third code by a delta-sigma modulation of the first code. The third circuit may be configured to generate the output clock signal in response to the third code. An accuracy of a frequency of the output clock signal may be determined by a current value of the second code.
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公开(公告)号：US10084457B2
公开(公告)日：2018-09-25
申请号：US15408655
申请日：2017-01-18
Applicant: Integrated Device Technology, Inc.
Inventor： Hui Li , Teck-Chuan Ng , Stephen E. Aycock
Abstract: An apparatus includes a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate a first code by counting a number of cycles of an input clock signal in a period determined by (i) an output clock signal and (ii) a second code. The second code may be variable. The second circuit may be configured to generate a third code by a delta-sigma modulation of the first code. The third circuit may be configured to generate the output clock signal (i) in response to the third code and (ii) within an accuracy determined the second code.
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4.发明授权Initiating operation of a timing device using a read only memory (ROM) or a one time programmable non volatile memory (OTP NVM) 有权使用只读存储器（ROM）或一次性可编程非易失性存储器（OTP NVM）启动定时装置的操作，公开(公告)号：US09495285B2
公开(公告)日：2016-11-15
申请号：US14488262
申请日：2014-09-16
Applicant: Integrated Device Technology, Inc.
CPC classification number: G06F12/0238 , G06F12/0638 , G06F2212/202 , G11C7/20 , G11C11/005 , G11C11/413
Abstract: The present invention provides a method and a programmable timing device that includes a timing device circuit for generating at least one timing signal, a static random access memory (SRAM) coupled to the timing device circuit, a read only memory (ROM) having a first timing device configuration stored therein, a one time programmable non volatile memory (OTP NVM) for storing a second timing device configuration and selection logic. The selection logic includes an output coupled to the SRAM, a first input coupled to the ROM and a second input coupled to the OTP NVM. The selection logic is operable to receive input indicating whether SRAM is to be loaded from the ROM or the OTP NVM, and operable to load either the first timing device configuration from the ROM or the second timing device configuration from the OTP NVM based on the input.
Abstract translation: 本发明提供了一种方法和可编程定时装置，其包括用于产生至少一个定时信号的定时装置电路，耦合到定时装置电路的静态随机存取存储器（SRAM），具有第一 存储其中的定时设备配置，用于存储第二定时设备配置和选择逻辑的一次性可编程非易失性存储器（OTP NVM）。 选择逻辑包括耦合到SRAM的输出，耦合到ROM的第一输入和耦合到OTP NVM的第二输入。 选择逻辑可操作以接收指示是否要从ROM或OTP NVM加载SRAM的输入，并且可操作以基于输入从OTP NVM加载来自ROM的第一定时设备配置或第二定时设备配置 。
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5.发明申请INITIATING OPERATION OF A TIMING DEVICE USING A READ ONLY MEMORY (ROM) OR A ONE TIME PROGRAMMABLE NON VOLATILE MEMORY (OTP NVM) 有权使用只读存储器（ROM）或一次性可编程非易失性存储器（OTP NVM）启动定时设备的操作公开(公告)号：US20160077958A1
公开(公告)日：2016-03-17
申请号：US14488262
申请日：2014-09-16
Applicant: Integrated Device Technology, Inc.
IPC: G06F12/02
CPC classification number: G06F12/0238 , G06F12/0638 , G06F2212/202 , G11C7/20 , G11C11/005 , G11C11/413
Abstract: The present invention provides a method and a programmable timing device that includes a timing device circuit for generating at least one timing signal, a static random access memory (SRAM) coupled to the timing device circuit, a read only memory (ROM) having a first timing device configuration stored therein, a one time programmable non volatile memory (OTP NVM) for storing a second timing device configuration and selection logic. The selection logic includes an output coupled to the SRAM, a first input coupled to the ROM and a second input coupled to the OTP NVM. The selection logic is operable to receive input indicating whether SRAM is to be loaded from the ROM or the OTP NVM, and operable to load either the first timing device configuration from the ROM or the second timing device configuration from the OTP NVM based on the input.
Abstract translation: 本发明提供了一种方法和可编程定时装置，其包括用于产生至少一个定时信号的定时装置电路，耦合到定时装置电路的静态随机存取存储器（SRAM），具有第一 存储在其中的定时设备配置，用于存储第二定时设备配置和选择逻辑的一次性可编程非易失性存储器（OTP NVM）。 选择逻辑包括耦合到SRAM的输出，耦合到ROM的第一输入和耦合到OTP NVM的第二输入。 选择逻辑可操作以接收指示是否要从ROM或OTP NVM加载SRAM的输入，并且可操作以基于输入从OTP NVM加载来自ROM的第一定时设备配置或第二定时设备配置 。
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Patent Agency Ranking
公开(公告)号：US10483982B2
公开(公告)日：2019-11-19
申请号：US16139340
申请日：2018-09-24
Applicant: Integrated Device Technology, Inc.
Inventor： Hui Li , Teck-Chuan Ng , Stephen E. Aycock
Abstract: An apparatus includes a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate a first code by counting a number of cycles of an input clock signal during a period. The period may be determined by an output clock signal and a second code. The second circuit may be configured to generate a third code by a delta-sigma modulation of the first code. The third circuit may be configured to generate the output clock signal in response to the third code. An accuracy of a frequency of the output clock signal may be determined by a current value of the second code.
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公开(公告)号：US09954516B1
公开(公告)日：2018-04-24
申请号：US14830698
申请日：2015-08-19
Applicant: Integrated Device Technology, Inc.
Inventor： Hui Li , Teck Chuan Ng
Abstract: A timing device that includes an OTP NVM, a first periodic signal generator operable to generate a periodic signal having a first frequency, a second periodic signal generator operable to generate a periodic signal having a frequency that is lower than the first frequency, and selection logic. In a first operating mode, the selection logic is configured to output the first periodic signal at an output terminal as long as a crystal clock feedback signal is received at the input terminal and output the second periodic signal when the crystal clock feedback signal is not received at the input terminal. In a second operating mode, the selection logic is configured to output the first periodic signal as long as a output enable signal is received at the input terminal and not provide any output at the output terminal when the output enable signal is not received at the input terminal.
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公开(公告)号：US10511344B1
公开(公告)日：2019-12-17
申请号：US16229542
申请日：2018-12-21
Applicant: Integrated Device Technology, Inc.
Inventor： Victor Korol , Hui Li , Roberto Aparicio Joo , Naveen Yanduru
Abstract: An apparatus comprises an input port, an output port, and a resonant receive switch circuit. The resonant receive switch circuit may be coupled between the input port and the output port. The resonant receive switch circuit may comprise a first switch, a second switch, and an input matching circuit. When the first and the second switches are in a non-conducting state, a signal at the input port is passed to the output port. When the first and the second switches are in a conducting state, the signal at the input port is prevented from reaching the output port.
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公开(公告)号：US20180205382A1
公开(公告)日：2018-07-19
申请号：US15408655
申请日：2017-01-18
Applicant: Integrated Device Technology, Inc.
Inventor： Hui Li , Teck-Chuan Ng , Stephen E. Aycock
Abstract: An apparatus includes a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate a first code by counting a number of cycles of an input clock signal in a period determined by (i) an output clock signal and (ii) a second code. The second code may be variable. The second circuit may be configured to generate a third code by a delta-sigma modulation of the first code. The third circuit may be configured to generate the output clock signal (i) in response to the third code and (ii) within an accuracy determined the second code.
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10.发明授权Controlling operation of a timing device using an OTP NVM to store timing device configurations in a RAM 有权使用OTP NVM控制定时设备的操作，以将定时设备配置存储在RAM中公开(公告)号：US09455045B1
公开(公告)日：2016-09-27
申请号：US14691472
申请日：2015-04-20
Applicant: Integrated Device Technology, Inc.
Inventor： Xiaohong Zheng , Hui Li
Abstract: The present invention provides a method and apparatus that includes a timing device circuit for generating a timing signal, a RAM coupled to the timing device circuit, an OTP NVM and selection logic. The RAM is operable upon receiving a burn address to read configuration data in the RAM beginning at the burn address and the OTP NVM is operable to burn the configuration data read from RAM into the OTP NVM. The OTP NVM is configured to read configuration data in the OTP NVM and the RAM is configured to store the configuration data from the OTP NVM beginning at an address in the RAM corresponding to a read start address to define a timing device configuration in the RAM.
Abstract translation: 本发明提供了一种方法和装置，其包括用于产生定时信号的定时装置电路，耦合到定时装置电路的RAM，OTP NVM和选择逻辑。 RAM可以在接收到刻录地址以从烧录地址开始读取RAM中的配置数据时操作，并且OTP NVM可操作地将从RAM读取的配置数据刻录到OTP NVM中。 OTP NVM被配置为读取OTP NVM中的配置数据，并且RAM被配置为从对应于读起始地址的RAM中的地址开始存储来自OTP NVM的配置数据，以定义RAM中的定时设备配置。
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