公开(公告)号：US20220229723A1

公开(公告)日：2022-07-21

申请号：US17711646

申请日：2022-04-01

Applicant: Intel Corporation

Inventor： Joshua B. Fryman ,  Byoungchan Oh ,  Jason Howard ,  Sai Dheeraj Polagani

IPC: G06F11/10

Abstract: Memory requests are protected by encoding memory requests to include error correction codes. A subset of bits in a memory request are compared to a pre-defined pattern to determine whether the subset of bits matches a pre-defined pattern, where a match indicates that a compression can be applied to the memory request. The error correction code is generated for the memory request and the memory request is encoded to remove the subset of bits, add the error correction code, and add at least one metadata bit to the memory request to generate a protected version of the memory request, where the at least one metadata bit identifies whether the compression was applied to the memory request.

公开(公告)号：US20240256283A1

公开(公告)日：2024-08-01

申请号：US18566068

申请日：2022-03-31

Applicant: Intel Corporation

Inventor： Joshua B. Fryman ,  Byoungchan Oh ,  Sai Dheeraj Polagani ,  Kevin P. Ma ,  Robert S. Pawlowski ,  Bharadwaj Coimbatore Krishnamurthy ,  Shruti Sharma ,  Smitha P. Vasantha Kumar ,  Jason Howard ,  Daniel S. Klowden

IPC: G06F9/38 ,  G06F11/34

CPC classification number: G06F9/3851 ,  G06F11/3409

Abstract: A system is provided that includes a set of graph processing cores and a set of dense compute cores. where the set of graph processing cores and the set of dense cores are interconnected in a network. The dense compute cores include offload queue circuitry to receive an offload request from the set of graph processing cores to handle dense compute workloads. Memory controllers are also provided in the system for use by the graph processing cores in reading and writing to memory in association with sparse graph applications. the memory controllers enhanced to efficiently handle memory transactions in sparse graph applications.

公开(公告)号：US11157359B2

公开(公告)日：2021-10-26

申请号：US17031772

申请日：2020-09-24

Applicant: Intel Corporation

Inventor： Byoungchan Oh ,  Wei Wu

IPC: G06F11/00 ,  G06F11/10 ,  H03M13/29 ,  H03M13/15

Abstract: Examples include techniques to improve implement an error correction codeword (ECC) scheme to protect data stored to a memory from both hard and random bit errors using a hybrid ECC scheme that includes generation of first and second codewords to protect the data.

公开(公告)号：US12158852B2

公开(公告)日：2024-12-03

申请号：US17358832

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Robert Pawlowski ,  Bharadwaj Krishnamurthy ,  Shruti Sharma ,  Byoungchan Oh ,  Jing Fang ,  Daniel Klowden ,  Jason Howard ,  Joshua Fryman

IPC: G06F13/28

Abstract: Systems, methods, and apparatuses for direct memory access instruction set architecture support for flexible dense compute using a reconfigurable spatial array are described. In one embodiment, a processor includes a first type of hardware processor core that includes a two-dimensional grid of compute circuits, a memory, and a direct memory access circuit coupled to the memory and the two-dimensional grid of compute circuits; and a second different type of hardware processor core that includes a decoder circuit to decode a single instruction into a decoded single instruction, the single instruction including a first field to identify a base address of two-dimensional data in the memory, a second field to identify a number of elements in each one-dimensional array of the two-dimensional data, a third field to identify a number of one-dimensional arrays of the two-dimensional data, a fourth field to identify an operation to be performed by the two-dimensional grid of compute circuits, and a fifth field to indicate the direct memory access circuit is to move the two-dimensional data indicated by the first field, the second field, and the third field into the two-dimensional grid of compute circuits and the two-dimensional grid of compute circuits is to perform the operation on the two-dimensional data according to the fourth field, and an execution circuit to execute the decoded single instruction according to the fields.

公开(公告)号：US11308006B2

公开(公告)日：2022-04-19

申请号：US16833322

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Byoungchan Oh ,  Sai Dheeraj Polagani ,  Joshua B. Fryman

IPC: G06F13/16 ,  G06F13/42 ,  G06F12/0879 ,  G11C11/4093 ,  G11C5/04 ,  G11C29/42

Abstract: An apparatus is described. The apparatus includes a rank of memory chips to couple to a memory channel. The memory channel is characterized as having eight transfers of eight bits of raw data per burst access. The rank of memory chips has first, second and third X4 memory chips. The X4 memory chips conform to a JEDEC dual data rate (DDR) memory interface specification. The first and second X4 memory chips are to couple to an eight bit raw data portion of the memory channel's data bus. The third X4 memory chip to couple to an error correction coding (ECC) information portion of the memory channel's data bus.