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公开(公告)号：US20200211261A1
公开(公告)日：2020-07-02
申请号：US16235744
申请日：2018-12-28
Applicant: Intel Corporation
Inventor： SCOTT JANUS , PRASOONKUMAR SURTI , KARTHIK VAIDYANATHAN , GABOR LIKTOR , CARSTEN BENTHIN , PHILIP LAWS
Abstract: Apparatus and method for general ray tracing queries. For example, one embodiment of an apparatus comprises: a hierarchical acceleration data structure generator to construct an acceleration data structure comprising a plurality of hierarchically arranged nodes associated with a graphics scene; traversal/intersection hardware logic to traverse one or more rays through the acceleration data structure to determine intersections between the one or more rays and one or more primitives within the hierarchical acceleration data structure; shape processing hardware logic to specify three dimensional (3D) shape data indicating one or more 3D shapes to be used to perform queries with respect to the hierarchical acceleration data structure; query processing hardware logic to execute queries comprising comparisons between nodes of the hierarchical acceleration data structure and the 3D shape data to generate a result indicating overlap between the 3D shapes and the nodes.
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公开(公告)号：US20210150800A1
公开(公告)日：2021-05-20
申请号：US17108774
申请日：2020-12-01
Applicant: Intel Corporation
Inventor： CARSTEN BENTHIN , INGO WALD , GABOR LIKTOR , JOHANNES GUENTHER , ELMOUSTAPHA OULD-AHMED-VALL
Abstract: An apparatus and method for performing BVH compression and decompression concurrently with stores and loads, respectively. For example, one embodiment comprises: bounding volume hierarchy (BVH) construction circuitry to build a BVH based on a set of input primitives, the BVH comprising a plurality of uncompressed coordinates; traversal/intersection circuitry to traverse one or more rays through the BVH and determine intersections with the set of input primitives using the uncompressed coordinates; store with compression circuitry to compress the BVH including the plurality of uncompressed coordinates to generate a compressed BVH with compressed coordinates and to store the compressed BVH to a memory subsystem; and load with decompression circuitry to decompress the BVH including the compressed coordinates to generate a decompressed BVH with the uncompressed coordinates and to load the decompressed BVH with uncompressed coordinates to a cache and/or a set of registers accessible by the traversal/intersection circuitry.
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公开(公告)号：US20200211252A1
公开(公告)日：2020-07-02
申请号：US16235893
申请日：2018-12-28
Applicant: Intel Corporation
Inventor： PRASOONKUMAR SURTI , CARSTEN BENTHIN , KARTHIK VAIDYANATHAN , PHILIP LAWS , SCOTT JANUS , SVEN WOOP
Abstract: Cluster of acceleration engines to accelerate intersections. For example, one embodiment of an apparatus comprises: a set of graphics cores to execute a first set of instructions of a primary graphics thread; a scalar cluster comprising a plurality of scalar execution engines; and a communication fabric interconnecting the set of graphics cores and the scalar cluster; the set of graphics cores to offload execution of a second set of instructions associated with ray traversal and/or intersection operations to the scalar cluster; the scalar cluster comprising a plurality of local memories, each local memory associated with one of the scalar execution engines, wherein each local memory is to store a portion of a hierarchical acceleration data structure required by an associated scalar execution engine to execute one or more of the second set of instructions; the plurality of scalar execution engines to store results of the execution of the second set of instructions in a memory accessible by the set of graphics cores; wherein the set of graphics cores are to process the results within the primary graphics thread.
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公开(公告)号：US20190318445A1
公开(公告)日：2019-10-17
申请号：US16236185
申请日：2018-12-28
Applicant: Intel Corporation
Inventor： CARSTEN BENTHIN , SVEN WOOP , INGO WALD
Abstract: Apparatus and method for compressing an acceleration data structure such as a bounding volume hierarchy (BVH). For example, one embodiment of a graphics processing apparatus comprises: one or more cores to execute graphics instructions including instructions to perform ray tracing operations; and compression circuitry to compress lowest level nodes of a hierarchical acceleration data structure comprising a plurality of hierarchically arranged nodes, each of the lowest level nodes comprising pointers to leaf data; the compression circuitry to quantize the lowest level nodes to generate quantized lowest level nodes and to store each quantized lowest level node and associated leaf data without the pointers to the leaf data.
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公开(公告)号：US20200211263A1
公开(公告)日：2020-07-02
申请号：US16235906
申请日：2018-12-28
Applicant: Intel Corporation
Inventor： SCOTT JANUS , PRASOONKUMAR SURTI , KARTHIK VAIDYANATHAN , ALEXEY SUPIKOV , GABOR LIKTOR , CARSTEN BENTHIN , PHILIP LAWS , MICHAEL DOYLE
Abstract: Apparatus and method for a hierarchical beam tracer. For example, one embodiment of an apparatus comprises: a beam generator to generate beam data associated with a beam projected into a graphics scene; a bounding volume hierarchy (BVH) generator to generate BVH data comprising a plurality of hierarchically arranged BVH nodes; a hierarchical beam-based traversal unit to determine whether the beam intersects a current BVH node and, if so, to responsively subdivide the beam into N child beams to test against the current BVH node and/or to traverse further down the BVH hierarchy to select a new BVH node, wherein the hierarchical beam-based traversal unit is to iteratively subdivide successive intersecting child beams and/or to continue to traverse down the BVH hierarchy until a leaf node is reached with which at least one final child beam is determined to intersect; the hierarchical beam-based traversal unit to generate a plurality of rays within the final child beam; and intersection hardware logic to perform intersection testing for any rays intersecting the leaf node, the intersection testing to determine intersections between the rays intersecting the leaf node and primitives bounded by the leaf node.
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Patent Agency Ranking
公开(公告)号：US20200211262A1
公开(公告)日：2020-07-02
申请号：US16235838
申请日：2018-12-28
Applicant: Intel Corporation
Inventor： KARTHIK VAIDYANATHAN , MICHAEL APODACA , THOMAS RAOUX , CARSTEN BENTHIN , KAI XIAO , CARSON BROWNLEE , JOSHUA BARCZAK
Abstract: An apparatus and method to execute ray tracing instructions. For example, one embodiment of an apparatus comprises execution circuitry to execute a dequantize instruction to convert a plurality of quantized data values to a plurality of dequantized data values, the dequantize instruction including a first source operand to identify a plurality of packed quantized data values in a source register and a destination operand to identify a destination register in which to store a plurality of packed dequantized data values, wherein the execution circuitry is to convert each packed quantized data value in the source register to a floating point value, to multiply the floating point value by a first value to generate a first product and to add the first product to a second value to generate a dequantized data value, and to store the dequantized data value in a packed data element location in the destination register.
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公开(公告)号：US20200211259A1
公开(公告)日：2020-07-02
申请号：US16235391
申请日：2018-12-28
Applicant: Intel Corporation
Inventor： MICHAEL APODACA , CARSTEN BENTHIN , KAI XIAO , CARSON BROWNLEE , TIMOTHY ROWLEY , JOSHUA BARCZAK , TRAVIS SCHLUESSLER
IPC: G06T15/06 , G06F7/14 , G06F16/901 , G06F9/38
Abstract: Apparatus and method for acceleration data structure refit. For example, one embodiment of an apparatus comprises: a ray generator to generate a plurality of rays in a first graphics scene; a hierarchical acceleration data structure generator to construct an acceleration data structure comprising a plurality of hierarchically arranged nodes including inner nodes and leaf nodes stored in a memory in a depth-first search (DFS) order; traversal hardware logic to traverse one or more of the rays through the acceleration data structure; intersection hardware logic to determine intersections between the one or more rays and one or more primitives within the hierarchical acceleration data structure; a node refit unit comprising circuitry and/or logic to read consecutively through at least the inner nodes in the memory in reverse DFS order to perform a bottom-up refit operation on the hierarchical acceleration data structure.
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8.发明申请公开(公告)号：US20200211151A1
公开(公告)日：2020-07-02
申请号：US16235604
申请日：2018-12-28
Applicant: Intel Corporation
Inventor： KARTHIK VAIDYANATHAN , SVEN WOOP , CARSTEN BENTHIN
Abstract: Apparatus and method for a compressed stack representation for a BVH. For example, one embodiment of an apparatus comprises: a ray generator to generate a plurality of rays in a first graphics scene; a bounding volume hierarchy (BVH) generator to construct a BVH comprising a plurality of hierarchically arranged nodes, wherein the BVH comprises a specified number of child nodes at a current BVH level beneath a parent node in the hierarchy; traversal/intersection circuitry to traverse one or more of the rays through the hierarchically arranged nodes of the BVH and intersect the one or more rays with primitives contained within the nodes; a short traversal stack of a fixed size comprising a specified number of entries fewer than the number of child nodes beneath the parent node, each entry associated with a child node at the current BVH level, the entries ordered from top to bottom within the short traversal stack based on a sorted distance of each respective child node, wherein each entry includes a field to indicate whether that entry is associated with a final child in the current BVH level; wherein the traversal/intersection circuitry is to process entries from the top of the traversal stack, removing entries as they are processed, the traversal/intersection circuitry to determine that a current entry is associated with the final child node at the current BVH level by reading a first value in the field.
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公开(公告)号：US20200043218A1
公开(公告)日：2020-02-06
申请号：US16056222
申请日：2018-08-06
Applicant: Intel Corporation
Inventor： KARTHIK VAIDYANATHAN , WON-JONG LEE , GABOR LIKTOR , JOHN G. GIERACH , PAWEL MAJEWSKI , PRASOONKUMAR SURTI , CARSTEN BENTHIN , Sven WOOP , THOMAS RAOUX
Abstract: Apparatus and method for programmable ray tracing with hardware acceleration on a graphics processor. For example, one embodiment of a graphics processor comprises shader execution circuitry to execute a plurality of programmable ray tracing shaders. The shader execution circuitry includes a plurality of single instruction multiple data (SIMD) execution units. Sorting circuitry regroups data associated with one or more of the programmable ray tracing shaders to increase occupancy for SIMD operations performed by the SIMD execution units; and fixed-function intersection circuitry coupled to the shader execution circuitry detects intersections between rays and bounding volume hierarchies (BVHs) and/or objects contained therein and to provide results indicating the intersections to the sorting circuitry.
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公开(公告)号：US20230297508A1
公开(公告)日：2023-09-21
申请号：US17699067
申请日：2022-03-18
Applicant: Intel Corporation
Inventor： TOBIAS ZIRR , CARSTEN BENTHIN
IPC: G06F12/0864 , G06F12/0837 , G06F12/02
CPC classification number: G06F12/0864 , G06F12/0837 , G06F12/0215
Abstract: Embodiments of the invention include acceleration hardware for performing texture lookups and for interpolation for textures backed by hashed memory layouts. In particular, on a texel fetch, a special texture addressing mode allows integer texel coordinates to be hashed and combined with dedicated hardware, to arrive at a pseudo-random memory address for each texel within the memory block allocated to back the respective sampled texture.
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