公开(公告)号：US09874910B2

公开(公告)日：2018-01-23

申请号：US14471572

申请日：2014-08-28

Applicant: Intel Corporation

Inventor： Tessil Thomas ,  Phani Kumar Kandula ,  Jayakrishna Guddeti ,  Chandra P. Joshi ,  Junaid F. Thaliyil ,  Pavithra Sampath

IPC: G06F1/24 ,  G06F13/42

CPC classification number: G06F1/24 ,  G06F13/4221 ,  Y02B70/123 ,  Y02B70/126 ,  Y02D10/14 ,  Y02D10/151

Abstract: In an embodiment, a processor includes at least one core to initiate a hot reset, and a peripheral device that is coupled to a root complex fabric via through the root port via an peripheral component interconnect express to on-chip system fabric (PCIE to OSF) bridge. The processor also includes a power control unit that includes reset logic to decouple the peripheral device from the root complex fabric responsive to initiation of the hot reset. After the peripheral device is decoupled from the root complex fabric, the reset logic is to assert a reset of the peripheral device while a first core of the at least one core is in operation. Other embodiments are described and claimed.

公开(公告)号：US09747245B2

公开(公告)日：2017-08-29

申请号：US14573738

申请日：2014-12-17

Applicant: Intel Corporation

Inventor： Jayakrishna Guddeti ,  Luke Chang ,  Junaid F. Thaliyil ,  Chandra P. Joshi

IPC: G06F13/12 ,  G06F13/00 ,  G06F13/42 ,  G06F11/30 ,  G06F13/16 ,  G06F13/24 ,  G06F13/40

CPC classification number: G06F13/4221 ,  G06F11/3027 ,  G06F13/1642 ,  G06F13/24 ,  G06F13/4022 ,  G06F13/4027

Abstract: In an embodiment, an apparatus comprises: a semiconductor die including but not limited to: at least one core to execute instructions; an agent to perform at least one function; a root complex including a first root port to interface to a first device to be coupled to the apparatus via a first interconnect and a second root port to interface to the agent via a bridge logic; and the bridge logic to interface the second root port to the agent, convert a first transaction from the first root port having a first format to a second format and communicate the first transaction having the second format to the agent. Other embodiments are described and claimed.

公开(公告)号：US20160179738A1

公开(公告)日：2016-06-23

申请号：US14573738

申请日：2014-12-17

Applicant: Intel Corporation

Inventor： Jayakrishna Guddeti ,  Luke Chang ,  Junaid F. Thaliyil ,  Chandra P. Joshi

IPC: G06F13/42 ,  G06F11/30 ,  G06F13/24 ,  G06F13/16 ,  G06F13/40

CPC classification number: G06F13/4221 ,  G06F11/3027 ,  G06F13/1642 ,  G06F13/24 ,  G06F13/4022 ,  G06F13/4027

Abstract: In an embodiment, an apparatus comprises: a semiconductor die including but not limited to: at least one core to execute instructions; an agent to perform at least one function; a root complex including a first root port to interface to a first device to be coupled to the apparatus via a first interconnect and a second root port to interface to the agent via a bridge logic; and the bridge logic to interface the second root port to the agent, convert a first transaction from the first root port having a first format to a second format and communicate the first transaction having the second format to the agent. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，一种装置包括：半导体管芯，包括但不限于：执行指令的至少一个核心; 执行至少一个功能的代理; 根组合件，其包括第一根端口以与第一设备接口以经由第一互连耦合到所述设备，以及第二根端口以经由桥逻辑与所述代理接口; 以及用于将第二根端口连接到代理的桥接逻辑，将具有第一格式的第一根端口的第一事务转换为第二格式，并将具有第二格式的第一事务传递给代理。 描述和要求保护其他实施例。

公开(公告)号：US20160062424A1

公开(公告)日：2016-03-03

申请号：US14471572

申请日：2014-08-28

Applicant: Intel Corporation

Inventor： Tessil Thomas ,  Phani Kumar Kandula ,  Jayakrishna Guddeti ,  Chandra P. Joshi ,  Junaid F. Thaliyil ,  Pavithra Sampath

IPC: G06F1/24 ,  G06F9/44 ,  G06F13/42

CPC classification number: G06F1/24 ,  G06F13/4221 ,  Y02B70/123 ,  Y02B70/126 ,  Y02D10/14 ,  Y02D10/151

Abstract: In an embodiment, a processor includes at least one core to initiate a hot reset, and a peripheral device that is coupled to a root complex fabric via through the root port via an peripheral component interconnect express to on-chip system fabric (PCIE to OSF) bridge. The processor also includes a power control unit that includes reset logic to decouple the peripheral device from the root complex fabric responsive to initiation of the hot reset. After the peripheral device is decoupled from the root complex fabric, the reset logic is to assert a reset of the peripheral device while a first core of the at least one core is in operation. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括至少一个核心来启动热复位，以及外围设备，其经由外部组件互连通过根端口与根组合架构耦合到片上系统架构（PCIE至OSF ）桥。 处理器还包括功率控制单元，其包括复位逻辑，以响应于热复位的启动来将外围设备与根复杂结构分离。 在外围设备与根复杂结构解耦之后，复位逻辑是在至少一个核心的第一核心正在运行时断言外围设备的复位。 描述和要求保护其他实施例。