公开(公告)号：US20230223361A1

公开(公告)日：2023-07-13

申请号：US18114123

申请日：2023-02-24

Applicant: Intel Corporation

Inventor： Dae-Woo KIM ,  Sujit SHARAN ,  Sairam AGRAHARAM

IPC: H01L23/58 ,  H01L21/66 ,  H01L23/498 ,  G01R31/27 ,  H01L23/522 ,  H01L23/544 ,  H01L23/00 ,  H01L25/18 ,  H01L25/065

CPC classification number: H01L23/585 ,  H01L22/32 ,  H01L23/49827 ,  G01R31/275 ,  H01L23/522 ,  H01L23/544 ,  H01L24/14 ,  H01L2924/1434 ,  H01L2224/32145 ,  H01L24/17 ,  H01L2223/54453 ,  H01L2224/1703 ,  H01L2224/81132 ,  H01L2924/1431 ,  H01L2924/3512 ,  H01L2223/54426 ,  H01L24/16 ,  H01L25/18 ,  H01L24/32 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/15192 ,  H01L2224/73267 ,  H01L24/92 ,  H01L2223/5442 ,  H01L2224/1403 ,  H01L2224/17153 ,  H01L2924/15313 ,  H01L24/73 ,  H01L2224/16145 ,  H01L2224/73253 ,  H01L25/0655 ,  H01L2224/14 ,  H01L2224/16227 ,  H01L24/81 ,  H01L2924/15153 ,  H01L2224/81203 ,  H01L2224/171 ,  H01L2224/17177

Abstract: Metal-free frame designs for silicon bridges for semiconductor packages and the resulting silicon bridges and semiconductor packages are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon, the substrate having a perimeter. A metallization structure is disposed on the insulating layer, the metallization structure including conductive routing disposed in a dielectric material stack. A first metal guard ring is disposed in the dielectric material stack and surrounds the conductive routing. A second metal guard ring is disposed in the dielectric material stack and surrounds the first metal guard ring. A metal-free region of the dielectric material stack surrounds the second metal guard ring. The metal-free region is disposed adjacent to the second metal guard ring and adjacent to the perimeter of the substrate.

公开(公告)号：US20230260884A1

公开(公告)日：2023-08-17

申请号：US18138512

申请日：2023-04-24

Applicant: Intel Corporation

Inventor： Arnab SARKAR ,  Sujit SHARAN ,  Dae-Woo KIM

IPC: H01L23/498 ,  H01L23/544 ,  H01L21/66 ,  H01L23/58 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/49827 ,  H01L23/544 ,  H01L22/32 ,  H01L23/585 ,  H01L25/0655 ,  H01L24/10 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/14 ,  H01L2224/16227 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/3512 ,  H01L24/16 ,  H01L25/18

Abstract: Guard ring designs enabling in-line testing of silicon bridges for semiconductor packages, and the resulting silicon bridges and semiconductor packages, are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon. A metallization structure is disposed on the insulating layer. The metallization structure incudes conductive routing disposed in a dielectric material stack. The semiconductor structure also includes a first metal guard ring disposed in the dielectric material stack and surrounding the conductive routing. The first metal guard ring includes a plurality of individual guard ring segments. The semiconductor structure also includes a second metal guard ring disposed in the dielectric material stack and surrounding the first metal guard ring. Electrical testing features are disposed in the dielectric material stack, between the first metal guard ring and the second metal guard ring.

公开(公告)号：US20230238339A1

公开(公告)日：2023-07-27

申请号：US18128954

申请日：2023-03-30

Applicant: Intel Corporation

Inventor： Dae-Woo KIM ,  Sujit SHARAN ,  Sairam AGRAHARAM

IPC: H01L23/58 ,  H01L23/538

CPC classification number: H01L23/585 ,  H01L23/5385 ,  H01L23/544

Abstract: Metal-free frame designs for silicon bridges for semiconductor packages and the resulting silicon bridges and semiconductor packages are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon, the substrate having a perimeter. A metallization structure is disposed on the insulating layer, the metallization structure including conductive routing disposed in a dielectric material stack. A first metal guard ring is disposed in the dielectric material stack and surrounds the conductive routing. A second metal guard ring is disposed in the dielectric material stack and surrounds the first metal guard ring. A metal-free region of the dielectric material stack surrounds the second metal guard ring. The metal-free region is disposed adjacent to the second metal guard ring and adjacent to the perimeter of the substrate.

公开(公告)号：US20180226330A1

公开(公告)日：2018-08-09

申请号：US15749462

申请日：2015-10-29

Applicant: Intel Corporation

Inventor： Dae-Woo KIM ,  Sujit SHARAN

IPC: H01L23/498 ,  H01L23/13 ,  H01L23/00

CPC classification number: H01L23/49827 ,  H01L23/13 ,  H01L23/48 ,  H01L23/49822 ,  H01L24/00 ,  H01L2224/14 ,  H01L2224/16225 ,  H01L2924/1431 ,  H01L2924/1435 ,  H01L2924/1517 ,  H01L2924/153

Abstract: Alternative surfaces for conductive pad layers of silicon bridges for semiconductor packages, and the resulting silicon bridges and semiconductor packages, are described. In an example, a semiconductor structure includes a substrate having a lower insulating layer disposed thereon. The substrate has a perimeter. A metallization structure is disposed on the lower insulating layer. The metallization structure includes conductive routing disposed in a dielectric material stack. First and second pluralities of conductive pads are disposed in a plane above the metallization structure. Conductive routing of the metallization structure electrically connects the first plurality of conductive pads with the second plurality of conductive pads. An upper insulating layer is disposed on the first and second pluralities of conductive pads. The upper insulating layer has a perimeter substantially the same as the perimeter of the substrate.

公开(公告)号：US20220130743A1

公开(公告)日：2022-04-28

申请号：US17573479

申请日：2022-01-11

Applicant: Intel Corporation

Inventor： Arnab SARKAR ,  Sujit SHARAN ,  Dae-Woo KIM

IPC: H01L23/498 ,  H01L23/544 ,  H01L21/66 ,  H01L23/58 ,  H01L25/065 ,  H01L23/00

Abstract: Guard ring designs enabling in-line testing of silicon bridges for semiconductor packages, and the resulting silicon bridges and semiconductor packages, are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon. A metallization structure is disposed on the insulating layer. The metallization structure incudes conductive routing disposed in a dielectric material stack. The semiconductor structure also includes a first metal guard ring disposed in the dielectric material stack and surrounding the conductive routing. The first metal guard ring includes a plurality of individual guard ring segments. The semiconductor structure also includes a second metal guard ring disposed in the dielectric material stack and surrounding the first metal guard ring. Electrical testing features are disposed in the dielectric material stack, between the first metal guard ring and the second metal guard ring.

公开(公告)号：US20250029908A1

公开(公告)日：2025-01-23

申请号：US18904780

申请日：2024-10-02

Applicant: Intel Corporation

Inventor： Arnab SARKAR ,  Sujit SHARAN ,  Dae-Woo KIM

IPC: H01L23/498 ,  H01L21/66 ,  H01L23/00 ,  H01L23/544 ,  H01L23/58 ,  H01L25/065 ,  H01L25/18

Abstract: Guard ring designs enabling in-line testing of silicon bridges for semiconductor packages, and the resulting silicon bridges and semiconductor packages, are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon. A metallization structure is disposed on the insulating layer. The metallization structure incudes conductive routing disposed in a dielectric material stack. The semiconductor structure also includes a first metal guard ring disposed in the dielectric material stack and surrounding the conductive routing. The first metal guard ring includes a plurality of individual guard ring segments. The semiconductor structure also includes a second metal guard ring disposed in the dielectric material stack and surrounding the first metal guard ring. Electrical testing features are disposed in the dielectric material stack, between the first metal guard ring and the second metal guard ring.

公开(公告)号：US20220285306A1

公开(公告)日：2022-09-08

申请号：US17825739

申请日：2022-05-26

Applicant: Intel Corporation

Inventor： Dae-Woo KIM ,  Ajay JAIN ,  Neha M. PATEL ,  Rodrick J. HENDRICKS ,  Sujit SHARAN

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/538

Abstract: An integrated circuit package is disclosed. The integrated circuit package comprises a first integrated circuit die and a second integrated circuit die. The integrated circuit package further includes a substrate, wherein both the first integrated circuit die and the second integrated circuit die are connected to the substrate. The substrate includes an interconnect bridge embedded within the substrate, wherein the interconnect bridge includes at least one metal trace component, wherein the metal trace component includes rounded corners on a bottom portion of the metal trace component.

公开(公告)号：US20210125942A1

公开(公告)日：2021-04-29

申请号：US17143142

申请日：2021-01-06

Applicant: Intel Corporation

Inventor： Dae-Woo KIM ,  Sujit SHARAN ,  Sairam AGRAHARAM

IPC: H01L23/58 ,  H01L23/498 ,  H01L23/544 ,  H01L21/66 ,  H01L23/00 ,  G01R31/27 ,  H01L23/522

Abstract: Metal-free frame designs for silicon bridges for semiconductor packages and the resulting silicon bridges and semiconductor packages are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon, the substrate having a perimeter. A metallization structure is disposed on the insulating layer, the metallization structure including conductive routing disposed in a dielectric material stack. A first metal guard ring is disposed in the dielectric material stack and surrounds the conductive routing. A second metal guard ring is disposed in the dielectric material stack and surrounds the first metal guard ring. A metal-free region of the dielectric material stack surrounds the second metal guard ring. The metal-free region is disposed adjacent to the second metal guard ring and adjacent to the perimeter of the substrate.

公开(公告)号：US20200013734A1

公开(公告)日：2020-01-09

申请号：US16576520

申请日：2019-09-19

Applicant: Intel Corporation

Inventor： Dae-Woo KIM ,  Sujit SHARAN ,  Sairam AGRAHARAM

IPC: H01L23/58 ,  H01L23/498 ,  H01L23/544 ,  H01L21/66 ,  H01L23/00 ,  G01R31/27 ,  H01L23/522

Abstract: Metal-free frame designs for silicon bridges for semiconductor packages and the resulting silicon bridges and semiconductor packages are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon, the substrate having a perimeter. A metallization structure is disposed on the insulating layer, the metallization structure including conductive routing disposed in a dielectric material stack. A first metal guard ring is disposed in the dielectric material stack and surrounds the conductive routing. A second metal guard ring is disposed in the dielectric material stack and surrounds the first metal guard ring. A metal-free region of the dielectric material stack surrounds the second metal guard ring. The metal-free region is disposed adjacent to the second metal guard ring and adjacent to the perimeter of the substrate.

公开(公告)号：US20250070056A1

公开(公告)日：2025-02-27

申请号：US18945109

申请日：2024-11-12

Applicant: Intel Corporation

Inventor： Dae-Woo KIM ,  Sujit SHARAN ,  Sairam AGRAHARAM

IPC: H01L23/58 ,  G01R31/27 ,  H01L21/66 ,  H01L23/00 ,  H01L23/14 ,  H01L23/498 ,  H01L23/522 ,  H01L23/538 ,  H01L23/544 ,  H01L25/065 ,  H01L25/18 ,  H10B80/00

Abstract: Metal-free frame designs for silicon bridges for semiconductor packages and the resulting silicon bridges and semiconductor packages are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon, the substrate having a perimeter. A metallization structure is disposed on the insulating layer, the metallization structure including conductive routing disposed in a dielectric material stack. A first metal guard ring is disposed in the dielectric material stack and surrounds the conductive routing. A second metal guard ring is disposed in the dielectric material stack and surrounds the first metal guard ring. A metal-free region of the dielectric material stack surrounds the second metal guard ring. The metal-free region is disposed adjacent to the second metal guard ring and adjacent to the perimeter of the substrate.