公开(公告)号：US20240118826A1

公开(公告)日：2024-04-11

申请号：US17963313

申请日：2022-10-11

Applicant: Intel Corporation

Inventor： Amlan Ghosh ,  Feroze Merchant ,  Jaydeep Kulkarni ,  John R. Riley

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: A memory device includes at least one bitcell coupled to a local bitline. The at least one bitcell includes multiple sets of a plurality of transistor devices. The first set of the plurality of transistor devices is configured to form a single write (1W) port for receiving digital data. The second set of the plurality of transistor devices is configured as an inverter pair. The inverter pair stores the digital data. The third set of the plurality of transistor devices is configured to form a single read (1R) port. The 1R port can be used to access the digital data stored at the inverter pair and output the digital data on the local bitline. The plurality of transistor devices includes an equal number of P-channel transistor devices and N-channel transistor devices.

公开(公告)号：US10374584B1

公开(公告)日：2019-08-06

申请号：US15916130

申请日：2018-03-08

Applicant: Intel Corporation

Inventor： Charles Augustine ,  Muhammad Khellah ,  Arvind Raman ,  Feroze Merchant ,  Ashish Choubal

IPC: H03K3/037 ,  G01R31/3185

Abstract: An apparatus comprising: a flip-flip comprising a master stage and a slave stage, wherein the slave stage is coupled to the master stage, wherein the master and slave stages are coupled to a first power supply rail; and a scan circuitry coupled to the slave stage of the flip-flip, wherein at least a portion of the scan circuitry is coupled to a second power supply rail.

公开(公告)号：US11320888B2

公开(公告)日：2022-05-03

申请号：US16124071

申请日：2018-09-06

Applicant: Intel Corporation

Inventor： Charles Augustine ,  Muhammad Khellah ,  Arvind Raman ,  Ashish Choubal ,  Karthik Subramanian ,  Abdullah Afzal ,  Feroze Merchant

IPC: G06F1/00 ,  G06F1/3234 ,  H02M3/157 ,  G06F1/324 ,  H02M1/00

Abstract: An apparatus is provided which comprises: a plurality of devices coupled to an input power supply rail and an output power supply rail; a first circuitry coupled to the plurality of devices, wherein the first circuitry is to turn on or off one or more devices of the plurality according to a control; and a second circuitry coupled to the first circuitry, wherein the second circuitry comprises an all-digital proportional-derivative mechanism to generate the control according to a digital representation of voltage on the output power supply rail.

公开(公告)号：US20200081512A1

公开(公告)日：2020-03-12

申请号：US16124071

申请日：2018-09-06

Applicant: Intel Corporation

Inventor： Charles Augustine ,  Muhammad Khellah ,  Arvind Raman ,  Ashish Choubal ,  Karthik Subramanian ,  Abdullah Afzal ,  Feroze Merchant

IPC: G06F1/32 ,  H02M3/157

Abstract: An apparatus is provided which comprises: a plurality of devices coupled to an input power supply rail and an output power supply rail; a first circuitry coupled to the plurality of devices, wherein the first circuitry is to turn on or off one or more devices of the plurality according to a control; and a second circuitry coupled to the first circuitry, wherein the second circuitry comprises an all-digital proportional-derivative mechanism to generate the control according to a digital representation of voltage on the output power supply rail.

公开(公告)号：US20240331761A1

公开(公告)日：2024-10-03

申请号：US18126680

申请日：2023-03-27

Applicant: Intel Corporation

Inventor： Charles Augustine ,  Amlan Ghosh ,  Seenivasan Subramaniam ,  Patrick Morrow ,  Muhammad M. Khellah ,  Feroze Merchant

IPC: G11C11/4096 ,  G11C11/4093 ,  G11C11/4094

CPC classification number: G11C11/4096 ,  G11C11/4093 ,  G11C11/4094

Abstract: An apparatus includes a first write bit line (WBL), a first P-channel metal oxide semiconductor (PMOS) transistor including a source coupled to the WBL, a first inverter including an input coupled to a drain of the first PMOS transistor, and a second PMOS transistor including a source coupled to an output of the first inverter. The first PMOS transistor and the second PMOS transistor are disposed in at least one PMOS layer configured between a first metal layer and a second metal layer. The register file circuit further includes a first via connecting a gate of the first PMOS transistor and a gate of the second PMOS transistor in the at least one PMOS layer to the first metal layer.

公开(公告)号：US20230170012A1

公开(公告)日：2023-06-01

申请号：US17538478

申请日：2021-11-30

Applicant: Intel Corporation

Inventor： Steve P. Ferrera ,  Mauricio J. Valverde Monge ,  Anik Basu ,  Feroze Merchant

IPC: G11C11/4091 ,  G11C11/4096 ,  G11C11/4094 ,  G11C11/408 ,  H03K19/173 ,  H03K19/20

CPC classification number: G11C11/4091 ,  G11C11/4096 ,  G11C11/4094 ,  G11C11/4085 ,  H03K19/1737 ,  H03K19/20

Abstract: Embodiments herein relate to circuitry which allows data to be processed and written back within an SRAM device. In a toggle operation, a memory cell is read and the bit at the complementary output node of a sense amplifier is written back to the memory cell. In a copy operation, a memory cell is read and the bit at the primary output node of the sense amplifier is written to another memory cell in the column. In another aspect, logic operations such as AND, OR, majority, AND-OR, OR-AND, and associated inverse operations can be performed within the SRAM device. This can involve writing data to one or more control memory cells in the same column as the data memory cells involved in the logic operation, and setting the respective word lines to be active concurrently.