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    Signal envelope detector, overload detector, receiver, base station and mobile device
    1.
    发明授权
    Signal envelope detector, overload detector, receiver, base station and mobile device 有权

    公开(公告)号：US12143073B2

    公开(公告)日：2024-11-12

    申请号：US17131962

    申请日：2020-12-23

    Applicant: Intel Corporation

    Inventor： Martin Clara ,  Giacomo Cascio

    IPC: H03F3/19 ,  H03F3/193 ,  H03F3/24 ,  H03F3/50

    Abstract: A signal envelope detector is provided. The signal envelope detector includes an input node configured to receive an input signal. Further, the signal envelope detector includes a capacitive voltage divider coupled to the input node and configured to generate an attenuated input signal by voltage division of the input signal. The signal envelope detector additionally includes a source follower transistor coupled between a first node configured to receive a first voltage supply signal and a second node configured to receive a second voltage supply signal. A gate terminal of the source follower transistor is coupled to the capacitive voltage divider and configured to receive the attenuated input signal. The signal envelope detector includes a rectifier circuit configured to receive and rectify an output signal of the source follower transistor. In addition, the signal envelope detector includes a low-pass filter coupled to the rectifier circuit and configured to generate an envelope signal indicative of a rectified envelope of the input signal by low-pass filtering of an output signal of the rectifier circuit.

    Reference buffer circuit, analog-to-digital converter system, receiver, base station and mobile device
    3.
    发明授权
    Reference buffer circuit, analog-to-digital converter system, receiver, base station and mobile device 有权

    公开(公告)号：US12074606B2

    公开(公告)日：2024-08-27

    申请号：US17131811

    申请日：2020-12-23

    Applicant: Intel Corporation

    Inventor： Daniel Gruber ,  Christian Lindholm ,  Martin Clara ,  Giacomo Cascio

    IPC: H03M1/08 ,  H03K19/003 ,  H03K19/0185 ,  H04B1/12

    CPC classification number: H03M1/0827 ,  H03K19/00384 ,  H03K19/018578 ,  H04B1/12

    Abstract: A reference buffer circuit for an analog-to-digital converter is provided. The reference buffer circuit includes a first input node configured to receive a first bias signal of a first polarity from a first signal line. Further, the reference buffer circuit includes a second input node configured to receive a second bias signal of a second polarity from a second signal line. Additionally, the reference buffer circuit includes a first output node configured to output a first reference signal of the first polarity. A first buffer amplifier is coupled between the first input node and the first output node. The reference buffer circuit includes in addition a second output node configured to output a second reference signal of the second polarity. A second buffer amplifier is coupled between the second input node and the second output node. Further, the reference buffer circuit includes a first coupling path comprising a first capacitive element. The first coupling path is coupled between the first output node and the second input node. In addition, the reference buffer circuit includes a second coupling path comprising a second capacitive element. The second coupling path is coupled between the second output node and the first input node.

    Input circuitry for an analog-to-digital converter, receiver, base station and method for operating an input circuitry for an analog-to-digital converter
    4.
    发明授权
    Input circuitry for an analog-to-digital converter, receiver, base station and method for operating an input circuitry for an analog-to-digital converter 有权

    公开(公告)号：US11489536B1

    公开(公告)日：2022-11-01

    申请号：US17358093

    申请日：2021-06-25

    Applicant: Intel Corporation

    Inventor： Martin Clara ,  Daniel Gruber ,  Giacomo Cascio ,  Albert Molina

    IPC: H03M1/10 ,  H04B1/12 ,  H04B1/48

    Abstract: Input circuitry for an analog-to-digital converter (ADC) is provided. The input circuitry includes a calibration signal source configured to output a calibration signal for the ADC and an analog circuitry configured to receive and process an analog input signal for the ADC. The analog circuitry is further configured to generate a combined signal by combining the analog input signal and the calibration signal. The input circuitry further includes a buffer amplifier coupled to the analog circuitry and configured to supply a buffered signal to the ADC based on the combined signal. Further, the input circuitry includes neutralization circuitry configured to generate, based on the calibration signal, a neutralization signal for mitigating an unwanted signal component related to a limited reverse isolation of the analog circuitry. The neutralization circuitry is further configured to supply the neutralization signal to at least one of an input node and an intermediate node of the analog circuitry.

    Buffer circuit, receiver, base station and mobile device
    5.
    发明授权
    Buffer circuit, receiver, base station and mobile device 有权

    公开(公告)号：US12132457B2

    公开(公告)日：2024-10-29

    申请号：US17131824

    申请日：2020-12-23

    Applicant: Intel Corporation

    Inventor： Martin Clara ,  Giacomo Cascio

    IPC: H03F3/45 ,  H03F1/30

    CPC classification number: H03F3/45192 ,  H03F1/303 ,  H03F2200/153

    Abstract: A buffer circuit is provided. The buffer circuit includes a Current Differencing Transconductance Amplifier (CDTA) comprising a first input node and a second input node each configured to receive a respective one of a first signal and a second signal. The buffer circuit further includes a first source follower circuit coupled to a first output node of the CDTA and configured to generate a first buffer output signal based on a first output signal of the CDTA. Additionally, the buffer circuit includes a second source follower circuit coupled to a second output node of the CDTA and configured to generate a second buffer output signal based on a second output signal of the CDTA. The buffer circuit further includes a first feedback path comprising at least one of a first resistive element and a first capacitive element. The first feedback path couples an output node of the first source follower circuit to the first input node of the CDTA. In addition, the buffer circuit includes a second feedback path comprising at least one of a second resistive element and a second capacitive element. The second feedback path couples an output node of the second source follower circuit to the second input node of the CDTA.

    Attenuator circuit, receiver, base station, mobile device and method for operating an attenuator circuit
    6.
    发明授权
    Attenuator circuit, receiver, base station, mobile device and method for operating an attenuator circuit 有权

    公开(公告)号：US12113500B2

    公开(公告)日：2024-10-08

    申请号：US17131809

    申请日：2020-12-23

    Applicant: Intel Corporation

    Inventor： Daniel Gruber ,  L Mark Elzinga ,  Martin Clara ,  Giacomo Cascio

    IPC: H03H11/24 ,  H04B1/16 ,  H04W88/08

    CPC classification number: H03H11/24 ,  H04B1/1607 ,  H04W88/08

    Abstract: An attenuator circuit is provided. The attenuator circuit includes a first input node and a second input node each configured to receive a respective one of a first input signal and a second input signal forming a differential input signal pair. Further, the attenuator circuit includes a first plurality of resistive elements coupled in series between the first input node and a first output node for outputting a first output signal. The attenuator circuit additionally includes a second plurality of resistive elements coupled in series between the second input node and a second output node for outputting a second output signal. In addition, the attenuator circuit includes a shunt path coupled to a first intermediate node and a second intermediate node. The first intermedia node is arranged between two resistive elements of the first plurality of resistive elements. The second intermedia node is arranged between two resistive elements of the second plurality of resistive elements. The shunt path comprises a switch circuit configured to selectively couple the first intermediate node and the second intermediate node based on one or more control signals.

    Input buffer circuit, analog-to-digital converter system, receiver, base station, mobile device and method for operating an input buffer circuit
    7.
    发明授权
    Input buffer circuit, analog-to-digital converter system, receiver, base station, mobile device and method for operating an input buffer circuit 有权

    公开(公告)号：US12015417B2

    公开(公告)日：2024-06-18

    申请号：US17131868

    申请日：2020-12-23

    Applicant: Intel Corporation

    Inventor： Daniel Gruber ,  Matteo Camponeschi ,  Christian Lindholm ,  Martin Clara ,  Giacomo Cascio

    IPC: H03M1/06 ,  H03K3/02 ,  H04B1/16

    CPC classification number: H03M1/0609 ,  H03K3/02 ,  H04B1/16

    Abstract: An input buffer circuit for an analog-to-digital converter is provided. The input buffer circuit includes a buffer amplifier. The buffer amplifier includes a first input node and a second input node each configured to receive a respective one of a first input signal and a second input signal forming a differential input signal pair for the analog-to-digital converter. The buffer amplifier further includes a first output node and a second output node each configured to output a respective one of a first buffered signal and a second buffered signal. In addition, the input buffer circuit includes feedback circuitry. The feedback circuitry is configured to generate, based on the first buffered signal and the second buffered signal, a first feedback signal and a second feedback signal for mitigating a respective unwanted signal component at the first input node and the second input node related to a limited reverse isolation of the amplifier buffer. The feedback circuitry is further configured to supply the first feedback signal to the first input node and the second feedback signal to the second input node.

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