公开(公告)号：US20240008290A1

公开(公告)日：2024-01-04

申请号：US17855626

申请日：2022-06-30

Applicant: INTEL CORPORATION

Inventor： Chia-Ching LIN ,  Shriram SHIVARAMAN ,  Kevin P. O'BRIEN ,  Ashish Verma PENUMATCHA ,  Chelsey DOROW ,  Kirby MAXEY ,  Carl H. NAYLOR ,  Sudarat LEE ,  Uygar E. AVCI ,  Sou-Chi CHANG

IPC: H01L27/11507 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L23/48

CPC classification number: H01L27/11507 ,  H01L29/516 ,  H01L29/6684 ,  H01L29/78391 ,  H01L23/481

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques directed to creating back end of line 2D transistors that include a metal-ferroelectric-metal-insulator-semiconductor structure used as a memory cell. In embodiments, a combination wet etch and dry etch process may be used to form the 2D transistors. Other embodiments may be described and/or claimed.

公开(公告)号：US20230420511A1

公开(公告)日：2023-12-28

申请号：US17850623

申请日：2022-06-27

Applicant: Intel Corporation

Inventor： Carl H. NAYLOR ,  Kirby MAXEY ,  Kevin P. O'BRIEN ,  Chelsey DOROW ,  Sudarat LEE ,  Ashish Verma PENUMATCHA ,  Uygar E. AVCI ,  Matthew V. METZ ,  Scott B. CLENDENNING ,  Chia-Ching LIN ,  Carly ROGAN ,  Arnab SEN GUPTA

IPC: H01L29/06 ,  H01L29/778 ,  H01L29/786 ,  H01L29/18 ,  H01L21/02

CPC classification number: H01L29/0673 ,  H01L29/778 ,  H01L29/78696 ,  H01L21/02568 ,  H01L21/02645 ,  H01L21/02598 ,  H01L21/02485 ,  H01L29/18

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for a transistor structure that includes stacked nanoribbons as a single crystal or monolayer, such as a transition metal dichalcogenide (TMD) layer, grown on a silicon wafer using a seeding material. Other embodiments may be described and/or claimed.

公开(公告)号：US20230420514A1

公开(公告)日：2023-12-28

申请号：US17852016

申请日：2022-06-28

Applicant: Intel Corporation

Inventor： Chelsey DOROW ,  Sudarat LEE ,  Kevin P. O'BRIEN ,  Ande KITAMURA ,  Ashish Verma PENUMATCHA ,  Carl H. NAYLOR ,  Kirby MAXEY ,  Scott B. CLENDENNING ,  Uygar E. AVCI ,  Chia-Ching LIN

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/18 ,  H01L29/786 ,  H01L29/778

CPC classification number: H01L29/0673 ,  H01L29/42392 ,  H01L29/18 ,  H01L29/78696 ,  H01L29/778

Abstract: Embodiments disclosed herein include transistor devices. In an embodiment, the transistor comprises a transition metal dichalcogenide (TMD) channel. In an embodiment, a two dimensional (2D) dielectric is over the TMD channel. In an embodiment, a gate metal is over the 2D dielectric.

公开(公告)号：US20230086499A1

公开(公告)日：2023-03-23

申请号：US17479155

申请日：2021-09-20

Applicant: Intel Corporation

Inventor： Kirby MAXEY ,  Ashish Verma PENUMATCHA ,  Kevin P. O'BRIEN ,  Chelsey DOROW ,  Uygar E. AVCI ,  Sudarat LEE ,  Carl NAYLOR ,  Tanay GOSAVI

IPC: H01L29/786 ,  H01L29/78

Abstract: Thin film transistors having fin structures integrated with two-dimensional (2D) channel materials are described. In an example, an integrated circuit structure includes a plurality of insulator fins above a substrate. A two-dimensional (2D) material layer is over the plurality of insulator fins. A gate dielectric layer is on the 2D material layer. A gate electrode is on the gate dielectric layer. A first conductive contact is on the 2D material layer adjacent to a first side of the gate electrode. A second conductive contact is on the 2D material layer adjacent to a second side of the gate electrode, the second side opposite the first side.

公开(公告)号：US20220149192A1

公开(公告)日：2022-05-12

申请号：US17093452

申请日：2020-11-09

Applicant: Intel Corporation

Inventor： Kirby MAXEY ,  Ashish Verma PENUMATCHA ,  Carl NAYLOR ,  Chelsey DOROW ,  Kevin P. O'BRIEN ,  Shriram SHIVARAMAN ,  Tanay GOSAVI ,  Uygar E. AVCI ,  Sudarat LEE

IPC: H01L29/76 ,  H01L29/24 ,  H01L29/786 ,  H01L29/66

Abstract: Thin film transistors having electrostatic double gates are described. In an example, an integrated circuit structure includes an insulator layer above a substrate. A first gate stack is on the insulator layer. A 2D channel material layer is on the first gate stack. A second gate stack is on a first portion of the 2D channel material layer, the second gate stack having a first side opposite a second side. A first conductive contact is adjacent the first side of the second gate stack, the first conductive contact on a second portion of the 2D channel material layer. A second conductive contact is adjacent the second side of the second gate stack, the second conductive contact on a third portion of the 2D channel material layer. A gate electrode of the first gate stack extends beneath a portion of the first conductive contact and beneath a portion of the second conductive contact.

公开(公告)号：US20240006521A1

公开(公告)日：2024-01-04

申请号：US17855620

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Chia-Ching LIN ,  Shriram SHIVARAMAN ,  Kevin P. O'BRIEN ,  Ashish Verma PENUMATCHA ,  Chelsey DOROW ,  Kirby MAXEY ,  Carl H. NAYLOR ,  Sudarat LEE ,  Uygar E. AVCI

IPC: H01L29/775 ,  H01L27/12 ,  H01L29/78 ,  H01L29/40 ,  H01L29/66 ,  H01L29/417

CPC classification number: H01L29/775 ,  H01L27/1255 ,  H01L29/78391 ,  H01L29/401 ,  H01L29/66969 ,  H01L29/41733 ,  H01L27/1259 ,  H01L29/0673

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques directed to creating back end of line 2D transistors that may be used as access transistors for a memory cell. In embodiments, a combination wet etch and dry etch process may be used to form the 2D transistors. Other embodiments may be described and/or claimed.

公开(公告)号：US20240006484A1

公开(公告)日：2024-01-04

申请号：US17855639

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Ashish Verma PENUMATCHA ,  Kevin P. O'BRIEN ,  Kirby MAXEY ,  Carl H. NAYLOR ,  Chelsey DOROW ,  Uygar E. AVCI ,  Matthew V. METZ ,  Sudarat LEE ,  Chia-Ching LIN ,  Sean T. MA

IPC: H01L29/06 ,  H01L29/778 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L29/78696 ,  H01L29/42392 ,  H01L29/778

Abstract: Embodiments disclosed herein include transistors and methods of forming transistors. In an embodiment, the transistor comprises a channel with a first end and a second end opposite from the first end, a first spacer around the first end of the channel, a second spacer around the second end of the channel, and a gate stack over the channel, where the gate stack is between the first spacer and the second spacer. In an embodiment, the transistor may further comprise a first extension contacting the first end of the channel; and a second extension contacting the first end of the channel. In an embodiment, the transistor further comprises conductive layers over the first extension and the second extension outside of the first spacer and the second spacer.

公开(公告)号：US20230420510A1

公开(公告)日：2023-12-28

申请号：US17850078

申请日：2022-06-27

Applicant: Intel Corporation

Inventor： Carl H. NAYLOR ,  Kirby MAXEY ,  Kevin P. O'BRIEN ,  Chelsey DOROW ,  Sudarat LEE ,  Ashish Verma PENUMATCHA ,  Uygar E. AVCI ,  Matthew V. METZ ,  Scott B. CLENDENNING ,  Jiun-Ruey CHEN ,  Chia-Ching LIN ,  Carly ROGAN

IPC: H01L29/06 ,  H01L29/778 ,  H01L29/786 ,  H01L29/18 ,  H01L21/02

CPC classification number: H01L29/0673 ,  H01L29/778 ,  H01L29/78696 ,  H01L29/18 ,  H01L21/02499 ,  H01L21/02568 ,  H01L21/02485

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques directed to creating a transistor structure by selectively growing a 2D TMD directly in a stacked channel configuration, such as a stacked nanowire or nanoribbon formation. In embodiments, this TMD growth may occur for all of the nanowires or nanoribbons in the transistor structure in one stage. Placement of a SAM on a plurality of dielectric layers within the transistor structure stack facilitates channel deposition and channel geometry in the stacked channel configuration. Other embodiments may be described and/or claimed.

公开(公告)号：US20230087668A1

公开(公告)日：2023-03-23

申请号：US17481250

申请日：2021-09-21

Applicant: Intel Corporation

Inventor： Chelsey DOROW ,  Kevin P. O'BRIEN ,  Carl NAYLOR ,  Kirby MAXEY ,  Sudarat LEE ,  Ashish Verma PENUMATCHA ,  Uygar E. AVCI

IPC: H01L29/786 ,  H01L29/10 ,  H01L29/423

Abstract: Thin film transistors having strain-inducing structures integrated with two-dimensional (2D) channel materials are described. In an example, an integrated circuit structure includes a two-dimensional (2D) material layer above a substrate. A gate stack is on the 2D material layer, the gate stack having a first side opposite a second side. A first gate spacer is on the 2D material layer and adjacent to the first side of the gate stack. A second gate spacer is on the 2D material layer and adjacent to the second side of the gate stack. The first gate spacer and the second gate spacer induce a strain on the 2D material layer. A first conductive structure is on the 2D material layer and adjacent to the first gate spacer. A second conductive structure is on the 2D material layer and adjacent to the second gate spacer.

公开(公告)号：US20210408288A1

公开(公告)日：2021-12-30

申请号：US16913835

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Kevin P. O'Brien ,  Carl NAYLOR ,  Chelsey DOROW ,  Kirby MAXEY ,  Tanay GOSAVI ,  Ashish Verma PENUMATCHA ,  Shriram SHIVARAMAN ,  Chia-Ching LIN ,  Sudarat LEE ,  Uygar E. AVCI

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/06 ,  H01L29/24 ,  H01L29/66

Abstract: Embodiments disclosed herein comprise semiconductor devices with two dimensional (2D) semiconductor channels and methods of forming such devices. In an embodiment, the semiconductor device comprises a source contact and a drain contact. In an embodiment, a 2D semiconductor channel is between the source contact and the drain contact. In an embodiment, the 2D semiconductor channel is a shell.