公开(公告)号：US11675326B2

公开(公告)日：2023-06-13

申请号：US17330738

申请日：2021-05-26

Applicant: Intel Corporation

Inventor： Nicolas A. Salhuana ,  Karthik Kumar ,  Thomas Willhalm ,  Francesc Guim Bernat ,  Narayan Ranganathan

IPC: G06F9/06 ,  G05B19/042 ,  H03K19/17732 ,  G06F8/41 ,  H03K19/17728

CPC classification number: G05B19/0426 ,  G06F8/44 ,  G06F8/456 ,  H03K19/17728 ,  H03K19/17732 ,  G05B2219/21109

Abstract: In one embodiment, an apparatus comprises a fabric controller of a first computing node. The fabric controller is to receive, from a second computing node via a network fabric that couples the first computing node to the second computing node, a request to execute a kernel on a field-programmable gate array (FPGA) of the first computing node; instruct the FPGA to execute the kernel; and send a result of the execution of the kernel to the second computing node via the network fabric.

公开(公告)号：US10949362B2

公开(公告)日：2021-03-16

申请号：US16456929

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Susanne M. Balle ,  Evan Custodio ,  Paul H. Dormitzer ,  Narayan Ranganathan

IPC: G06F13/16 ,  G06F3/06 ,  G06F13/40 ,  G06F21/60

Abstract: Technologies for facilitating remote memory requests in accelerator devices are disclosed. The accelerator device includes circuitry to receive, from a kernel of the present accelerator device, a request through an application programming interface exposed to a high level software language in which the kernel of the present accelerator device is implemented, to establish a logical communication path between the kernel of the present accelerator device and a target accelerator device kernel, based on one or more physical communication paths. The communication protocol supported by the accelerator device may allow kernels operating on the accelerator device to send memory requests for memory locations at remote devices, with the communication protocol performing all of the operations necessary to carry out the memory request.

公开(公告)号：US10608956B2

公开(公告)日：2020-03-31

申请号：US14973155

申请日：2015-12-17

Applicant: Intel Corporation

Inventor： Francesc Cesc Guim Bernat ,  Karthik Kumar ,  Thomas Willhalm ,  Raj K. Ramanujan ,  Narayan Ranganathan

IPC: H04L12/931 ,  H04L1/00 ,  H04L12/18 ,  H04L12/26 ,  H04L12/927 ,  H04L12/24

Abstract: Described herein are devices and techniques for distributing application data. A device can communicate with one or more hardware switches. The device can receive, from a software stack, a multicast message including a constraint that indicates how application data is to be distributed. The constraint including a listing of the set of nodes and a number of nodes to which the application data is to be distributed. The device may receive, from the software stack, the application data for distribution to a plurality of nodes. The plurality of nodes being a subset of the set of nodes equaling the number of nodes. The device may select the plurality of nodes from the set of nodes. The device also may distribute a copy of the application data to the plurality of nodes based on the constraint. Also described are other embodiments.

公开(公告)号：US10474596B2

公开(公告)日：2019-11-12

申请号：US14749893

申请日：2015-06-25

Applicant: Intel Corporation

Inventor： Sarathy Jayakumar ,  Ashok Raj ,  John G. Holm ,  Narayan Ranganathan ,  Mohan J. Kumar ,  Sergiu D. Ghetie

IPC: G06F13/24 ,  G06F1/3287 ,  G06F9/4401 ,  G06F1/3228

Abstract: In one embodiment, a processor includes a plurality of cores including a first core to be reserved for execution in a protected domain, the first core to be hidden from an operating system. The processor may further include a filter coupled to the plurality of cores, where the filter includes a plurality of fields each associated with one of the plurality of cores to indicate whether an interrupt of the protected domain is to be directed to the corresponding core. Other embodiments are described and claimed.

公开(公告)号：US20190065083A1

公开(公告)日：2019-02-28

申请号：US15858557

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Sujoy Sen ,  Susanne M. Balle ,  Narayan Ranganathan ,  Evan Custodio ,  Paul H. Dormitzer ,  Francesc Guim Bernat

IPC: G06F3/06 ,  G06F21/62

Abstract: Technologies for providing efficient access to pooled accelerator devices include an accelerator sled. The accelerator sled includes an accelerator device and a controller connected to the accelerator device. The controller is to provide, to a compute sled, accelerator abstraction data. The accelerator abstraction data represents the accelerator device as one or more logical devices, each logical device having one or more memory regions accessible by the compute sled, and defines an access mode usable to access each corresponding memory region. The controller is further to receive, from the compute sled, a request to perform an operation on an identified memory region of the accelerator device with a corresponding access mode. Additionally, the controller is to convert the request from a first format to a second format that is different from the second format and is usable by the accelerator device to perform the operation. Additionally, the controller is to perform, in response to the request, the operation on the identified memory region of the accelerator device with the corresponding access mode. Other embodiments are also described and claimed.

公开(公告)号：US10116518B2

公开(公告)日：2018-10-30

申请号：US15599087

申请日：2017-05-18

Applicant: Intel Corporation

Inventor： Ramamurthy Krithivas ,  Narayan Ranganathan ,  Mohan J. Kumar ,  John C. Leung

IPC: H04L12/24 ,  H04L12/855 ,  H04L29/12

Abstract: Mechanisms to enable management controllers to learn the control plane hierarchy in data center environments. The data center is configured in a physical hierarchy including multiple pods, racks, trays, and sleds and associated switches. Management controllers at various levels in a control plane hierarchy and associated with switches in the physical hierarchy are configured to add their IP addresses to DHCP (Dynamic Host Control Protocol) responses that are generated by a DCHP server in response to DCHP requests for IP address requests initiated by DHCP clients including manageability controllers, compute nodes and storage nodes in the data center. As the DCHP response traverses each of multiple switches along a forwarding path from the DCHP server to the DHCP client, an IP address of the manageability controller associated with the switch is inserted. Upon receipt at the DHCP client, the inserted IP addresses are extracted and used to automate learning of the control plane hierarchy.

公开(公告)号：US09396059B2

公开(公告)日：2016-07-19

申请号：US14135570

申请日：2013-12-19

Applicant: INTEL CORPORATION

Inventor： Ashok Raj ,  Mohan Kumar ,  Narayan Ranganathan

IPC: G06F11/00 ,  G06F11/07 ,  G06F11/30

CPC classification number: G06F11/0793 ,  G06F11/0706 ,  G06F11/0766 ,  G06F11/0787 ,  G06F11/30 ,  G06F11/3003

Abstract: A computing system can include a platform firmware to monitor hardware errors and to notify an operating system when a corrective action is to be performed to address a hardware error. The computing system can also include an extended error log to describe a hardware error. The computing system can further include an action record to direct the operating system to perform the corrective action to address the hardware error.

Abstract translation: 计算系统可以包括用于监视硬件错误的平台固件，并且当执行纠正措施以解决硬件错误时通知操作系统。 计算系统还可以包括扩展错误日志来描述硬件错误。 计算系统还可以包括动作记录，以指示操作系统执行纠正措施来解决硬件错误。

公开(公告)号：US20240054011A1

公开(公告)日：2024-02-15

申请号：US18233308

申请日：2023-08-12

Applicant: Intel Corporation

Inventor： Rajesh M. Sankaran ,  Philip R. Lantz ,  Narayan Ranganathan ,  Saurabh Gayen ,  Sanjay Kumar ,  Nikhil Rao ,  Dhananjay A. Joshi ,  Hai Ming Khor ,  Utkarsh Y. Kakaiya

IPC: G06F9/48 ,  G06F9/50 ,  G06F12/0802

CPC classification number: G06F9/4881 ,  G06F9/5027 ,  G06F12/0802

Abstract: Methods and apparatus relating to data streaming accelerators are described. In an embodiment, a hardware accelerator such as a Data Streaming Accelerator (DSA) logic circuitry performs data movement and/or data transformation for data to be transferred between a processor (having one or more processor cores) and a storage device. Other embodiments are also disclosed and claimed.

公开(公告)号：US20190007334A1

公开(公告)日：2019-01-03

申请号：US15639641

申请日：2017-06-30

Applicant: INTEL CORPORATION

Inventor： Francesc Guim Bernat ,  Kshitij A. Doshi ,  Mark A. Schmisseur ,  Narayan Ranganathan ,  John Chun Kwok Leung

IPC: H04L12/911 ,  G06F13/40 ,  G06F9/455 ,  H04L12/40

Abstract: A host fabric interface (HFI) apparatus, including: an HFI to communicatively couple to a fabric; and a remote hardware acceleration (RHA) engine to: query an orchestrator via the fabric to identify a remote resource having an accelerator; and send a remote accelerator request to the remote resource via the fabric.

公开(公告)号：US10157142B2

公开(公告)日：2018-12-18

申请号：US15280965

申请日：2016-09-29

Applicant: INTEL CORPORATION

Inventor： Ashok Raj ,  Sivakumar Radhakrishnan ,  Dan J. Williams ,  Vishal Verma ,  Narayan Ranganathan ,  Chet R. Douglas

IPC: G06F12/00 ,  G06F12/10 ,  G06F3/06

Abstract: In one embodiment, a block data transfer interface employing offload data transfer engine in accordance with the present description includes an offload data transfer engine executing a data transfer command set to transfer a block of data in a transfer data path from a source memory to a new region of a destination memory, wherein the transfer data path bypasses a central processing unit to minimize or reduce involvement of the central processing unit in the block transfer. In response to a successful transfer indication, a logical address is re-mapped to a physical address of the new region of the destination memory, instead of a physical address of the original region of the destination memory. In one embodiment, the re-mapping is performed by a central processing unit. In another embodiment, the re-mapping is performed by the offload data transfer engine. Other aspects are described herein.