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    Technologies for network discovery
    1.
    发明授权
    Technologies for network discovery 有权

    公开(公告)号：US11362904B2

    公开(公告)日：2022-06-14

    申请号：US16957626

    申请日：2019-02-21

    Applicant: INTEL CORPORATION

    Inventor： Mrittika Ganguli ,  Dinesh Kumar ,  Robert Valiquette ,  Yadong Li ,  Mohan Kumar

    IPC: H04L41/12 ,  H04L12/46

    Abstract: Technologies for enhanced network discovery and configuration include a network with a fabric manager and multiple network devices. A network device requests platform information from a management controller and receives the platform information via a sideband interface. The network device broadcasts a discovery message indicative of the platform information on a link layer network. The fabric manager discovers the network topology with an enhanced link layer discovery protocol and creates a vPOD in the network. The vPOD includes an application network with multiple racks. The fabric manager creates a tagged network domain for the vPOD. The fabric manager sends an out-of-band configuration command to the network device with a tag associated with the vPOD. After receiving the out-of-band configuration command, the network device receives a packet, compares domain metadata of the packet to the tag received from the fabric manager, and routes the packet. Other embodiments are described and claimed.

    Unified FPGA view to a composed host
    2.
    发明授权
    Unified FPGA view to a composed host 有权

    公开(公告)号：US11182324B2

    公开(公告)日：2021-11-23

    申请号：US16905395

    申请日：2020-06-18

    Applicant: Intel Corporation

    Inventor： Mohan Kumar ,  Murugasamy Nachimuthu

    IPC: G06F13/40 ,  G06F9/455 ,  G06F15/78 ,  G06F9/50

    Abstract: Mechanisms for Field Programmable Gate Array (FPGA) chaining and unified FPGA views to a composed system hosts and associated methods, apparatus, systems and software A rack is populated with pooled system drawers including pooled compute drawers and pooled FPGA drawers communicatively coupled via input-output (IO) cables. The FPGA resources in the pooled system drawers are enumerated, identifying a location of type of each FPGA and whether it is a chainable FPGA. Intra-drawer chaining mechanisms are identified for the chainable FPGAs in each pooled compute and pooled FPGA drawer. Inter-drawer chaining mechanism are also identified for chaining FPGAs in separate pooled system drawers. The enumerated FPGA and chaining mechanism data is aggregated to generate a unified system view of the FPGA resources and their chaining mechanisms. Based on available compute nodes and FPGAs in the unified system view, new compute nodes are composed using chained FPGAs. The chained FPGAs are exposed to a hypervisor or operating system virtualization layer, or to an operating system hosted by the composed compute node as a virtual monolithic FPGA or multiple local FPGAs.

    Technologies for accelerating edge device workloads
    6.
    发明授权
    Technologies for accelerating edge device workloads 有权

    公开(公告)号：US10541942B2

    公开(公告)日：2020-01-21

    申请号：US15941943

    申请日：2018-03-30

    Applicant: Intel Corporation

    Inventor： Francesc Guim Bernat ,  Anil Rao ,  Suraj Prabhakaran ,  Mohan Kumar ,  Karthik Kumar

    IPC: H04L12/947 ,  H04L12/66 ,  H04L12/801 ,  H04L12/931

    Abstract: Technologies for accelerating edge device workloads at a device edge network include a network computing device which includes a processor platform that includes at least one processor which supports a plurality of non-accelerated function-as-a-service (FaaS) operations and an accelerated platform that includes at least one accelerator which supports a plurality of accelerated FaaS (AFaaS) operation. The network computing device is configured to receive a request to perform a FaaS operation, determine whether the received request indicates that an AFaaS operation is to be performed on the received request, and identify compute requirements for the AFaaS operation to be performed. The network computing device is further configured to select an accelerator platform to perform the identified AFaaS operation and forward the received request to the selected accelerator platform to perform the identified AFaaS operation. Other embodiments are described and claimed.

    Deployment of BIOS to operating system data exchange
    9.
    发明授权
    Deployment of BIOS to operating system data exchange 有权

    公开(公告)号：US11809878B2

    公开(公告)日：2023-11-07

    申请号：US16790203

    申请日：2020-02-13

    Applicant: Intel Corporation

    Inventor： Sarathy Jayakumar ,  Mohan Kumar

    IPC: G06F9/445 ,  G06F13/16 ,  G06F16/22 ,  G06F9/4401 ,  G06F8/65

    CPC classification number: G06F9/44505 ,  G06F8/65 ,  G06F9/4401 ,  G06F9/4411 ,  G06F13/1668 ,  G06F16/2228

    Abstract: Systems, apparatuses and methods may provide for technology that stores first hardware related data to a basic input output system (BIOS) memory area and generates a mailbox data structure, wherein the mailbox data structure includes a first identifier-pointer pair associated with the first hardware related data. Additionally, the technology may generate an operating system (OS) interface table, wherein the OS interface table includes a pointer to the mailbox data structure. In one example, the technology also stores second hardware related data to the BIOS memory area at runtime and adds a second identifier-pointer pair to the mailbox data structure at runtime, wherein the second identifier-pointer pair is associated with the second hardware related data.

    Technologies for accelerating edge device workloads
    10.
    发明授权
    Technologies for accelerating edge device workloads 有权

    公开(公告)号：US11159454B2

    公开(公告)日：2021-10-26

    申请号：US16748232

    申请日：2020-01-21

    Applicant: Intel Corporation

    Inventor： Francesc Guim Bernat ,  Anil Rao ,  Suraj Prabhakaran ,  Mohan Kumar ,  Karthik Kumar

    IPC: H04L12/947 ,  H04L12/66 ,  H04L12/801 ,  H04L12/931 ,  H04L12/24

    Abstract: Technologies for accelerating edge device workloads at a device edge network include a network computing device which includes a processor platform that includes at least one processor which supports a plurality of non-accelerated function-as-a-service (FaaS) operations and an accelerated platform that includes at least one accelerator which supports a plurality of accelerated FaaS (AFaaS) operation. The network computing device is configured to receive a request to perform a FaaS operation, determine whether the received request indicates that an AFaaS operation is to be performed on the received request, and identify compute requirements for the AFaaS operation to be performed. The network computing device is further configured to select an accelerator platform to perform the identified AFaaS operation and forward the received request to the selected accelerator platform to perform the identified AFaaS operation. Other embodiments are described and claimed.

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