公开(公告)号：US20250079399A1

公开(公告)日：2025-03-06

申请号：US18460918

申请日：2023-09-05

Applicant: Intel Corporation

Inventor： Sagar Suthram ,  Wilfred Gomes ,  Ravindranath Vithal Mahajan ,  Debendra Mallik ,  Nitin A. Deshpande ,  Pushkar Sharad Ranade ,  Abhishek A. Sharma

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/498

Abstract: Embodiments of a microelectronic assembly may include a first integrated circuit (IC) die having a first surface, a second surface opposite the first surface, and a third surface orthogonal to the first and second surfaces, the first IC die including an active region including a capacitor; and a metallization stack including a first conductive trace electrically coupled to a first conductor of the capacitor and a second conductive trace electrically coupled to a second conductor of the capacitor, wherein the first conductive trace and the second conductive trace are parallel to the first and second surfaces and exposed at the third surface; and a second IC die including a fourth surface, where the first conductive trace and the second conductive trace at the third surface of the first IC die are electrically coupled to the fourth surface of the second IC die by interconnects.

公开(公告)号：US20250079263A1

公开(公告)日：2025-03-06

申请号：US18460931

申请日：2023-09-05

Applicant: Intel Corporation

Inventor： Sagar Suthram ,  Debendra Mallik ,  Wilfred Gomes ,  Pushkar Sharad Ranade ,  Nitin A. Deshpande ,  Ravindranath Vithal Mahajan ,  Abhishek A. Sharma

IPC: H01L23/473 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

Abstract: Embodiments of a microelectronic assembly may include a first integrated circuit (IC) die having a first surface, a second surface opposite the first surface, and a third surface orthogonal to the first and second surfaces, the first IC die including a substrate with a microchannel, and a metallization stack with a conductive trace that is parallel to the first and second surfaces and exposed at the third surface; and a second IC die having a fourth surface, wherein the conductive trace exposed at the third surface of the first IC die is electrically coupled to the fourth surface of the second IC die by an interconnect.

公开(公告)号：US12113023B2

公开(公告)日：2024-10-08

申请号：US17126502

申请日：2020-12-18

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Nitin A. Deshpande

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L23/5383 ,  H01L21/4857 ,  H01L23/49822 ,  H01L24/13 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0655 ,  H01L2224/81203

Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

公开(公告)号：US20240136292A1

公开(公告)日：2024-04-25

申请号：US18400761

申请日：2023-12-29

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Edvin Cetegen ,  Anurag Tripathi ,  Nitin A. Deshpande

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/5381 ,  H01L21/4853 ,  H01L21/563 ,  H01L23/3185 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/18161

Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

公开(公告)号：US20220342150A1

公开(公告)日：2022-10-27

申请号：US17237375

申请日：2021-04-22

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Xiaoqian Li ,  Tarek A. Ibrahim ,  Ravindranath Vithal Mahajan ,  Nitin A. Deshpande

IPC: G02B6/122 ,  G02B6/12

Abstract: Photonic packages and device assemblies that include photonic integrated circuits (PICs) coupled to optical lenses on lateral sides of the PICs. An example photonic package comprises a package support, an integrated circuit (IC), an insulating material, a PIC having an active side and a lateral side substantially perpendicular to the active side. At least one optical structure is on the active side. A substantial portion of the active side is in contact with the insulating material, and the PIC is electrically coupled to the package support and to the IC. The photonic package further includes an optical lens coupled to the PIC on the lateral side. In some embodiments, the photonic package further includes an interposer between the PIC or the IC and the package support.

公开(公告)号：US20220199480A1

公开(公告)日：2022-06-23

申请号：US17129135

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Xiaoxuan Sun ,  Nitin A. Deshpande ,  Sairam Agraharam

IPC: H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

公开(公告)号：US20210391273A1

公开(公告)日：2021-12-16

申请号：US16902777

申请日：2020-06-16

Applicant: Intel Corporation

Inventor： Manish Dubey ,  Omkar G. Karhade ,  Nitin A. Deshpande ,  Jinhe Liu ,  Sairam Agraharam ,  Mohit Bhatia ,  Edvin Cetegen

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/00

Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

公开(公告)号：US20210391268A1

公开(公告)日：2021-12-16

申请号：US16902910

申请日：2020-06-16

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Nitin A. Deshpande ,  Mohit Bhatia ,  Debendra Mallik

IPC: H01L23/538 ,  H01L25/18 ,  H01L25/065 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48

Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

公开(公告)号：US20210288035A1

公开(公告)日：2021-09-16

申请号：US16816669

申请日：2020-03-12

Applicant: Intel Corporation

Inventor： Thomas Liljeberg ,  Andrew C. Alduino ,  Ravindranath Vithal Mahajan ,  Ling Liao ,  Kenneth Brown ,  James Jaussi ,  Bharadwaj Parthasarathy ,  Nitin A. Deshpande

IPC: H01L25/16 ,  H01L23/00 ,  G02B6/42 ,  H01L23/367 ,  H04B10/40

Abstract: Embodiments may relate to a microelectronic package that includes a package substrate with an active bridge positioned therein. An active die may be coupled with the package substrate, and communicatively coupled with the active bridge. A photonic integrated circuit (PIC) may also be coupled with the package substrate and communicatively coupled with the active bridge. Other embodiments may be described or claimed.

公开(公告)号：US10192810B2

公开(公告)日：2019-01-29

申请号：US13930082

申请日：2013-06-28

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Nitin A. Deshpande ,  Rajendra C. Dias ,  Edvin Cetegen ,  Lars D. Skoglund

IPC: H01L23/22 ,  H01L23/24 ,  H01L23/485 ,  H01L21/56 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065 ,  H01L25/18

Abstract: Underfill material flow control for reduced die-to-die spacing in semiconductor packages and the resulting semiconductor packages are described. In an example, a semiconductor apparatus includes first and second semiconductor dies, each having a surface with an integrated circuit thereon coupled to contact pads of an uppermost metallization layer of a common semiconductor package substrate by a plurality of conductive contacts, the first and second semiconductor dies separated by a spacing. A barrier structure is disposed between the first semiconductor die and the common semiconductor package substrate and at least partially underneath the first semiconductor die. An underfill material layer is in contact with the second semiconductor die and with the barrier structure, but not in contact with the first semiconductor die.