公开(公告)号：US20240388529A1

公开(公告)日：2024-11-21

申请号：US18665632

申请日：2024-05-16

Applicant: Intel Corporation

Inventor： Eliel LOUZOUN ,  Manasi DEVAL ,  Stephen DOYLE ,  Noam ELATI ,  Patrick FLEMING ,  Gregory BOWERS

IPC: H04L45/74 ,  H04L47/36 ,  H04L49/90

Abstract: An apparatus, a method, and a computer program for generating data packets according to a transport protocol from an application buffer comprising a plurality of data streams is provided. The apparatus comprises an input circuit configured to receive metadata comprising at least one of information about data packet types supported by the transport protocol, information about an offset and a length of the supported data packet types, and information about possible stream header start positions, possible payload start positions and possible offsets in the data streams. Further, the apparatus comprises a parsing circuit configured to identify offsets in an application buffer as possible segmentation points based on the metadata, to segment the application buffer at the possible segmentation points into segments for data packets, and to generate data packets according to the transport protocol based on the segments. Furthermore, an apparatus, a method and a computer program for processing the application buffer is provided.

公开(公告)号：US20230333921A1

公开(公告)日：2023-10-19

申请号：US18112382

申请日：2023-02-21

Applicant: Intel Corporation

Inventor： Noam ELATI ,  Piotr UMINSKI ,  Boris KLEIMAN ,  Lloyd DCRUZ ,  Bradley A. BURRES ,  Salma Mirza JOHNSON ,  Thomas E. WILLIS ,  Duane E. GALBI

IPC: G06F9/54 ,  G06F9/455

CPC classification number: G06F9/542 ,  G06F9/45533

Abstract: Examples described herein relate to a host interface and circuitry. In some examples, the circuitry, when coupled to a physical device, is to: perform operations of a hypervisor. In some examples, the host interface is configured to route first communications to the circuitry instead of the physical device and route second communications to the physical device. In some examples, the physical device is accessible as a virtual device via the host interface.

公开(公告)号：US20220006750A1

公开(公告)日：2022-01-06

申请号：US17475197

申请日：2021-09-14

Applicant: Intel Corporation

Inventor： Sarig LIVNE ,  Noam ELATI ,  Hemanth KRISHNAN ,  Venkidesh KRISHNA IYER ,  Adam CONYERS ,  Michael G. LEFEVRE

IPC: H04L12/851 ,  H04L12/853 ,  H04L12/801 ,  H04L12/26

Abstract: Examples described herein relate to a network interface device comprising a packet transmission scheduler. In some examples, the packet transmission scheduler is to: perform packet transmit arbitration among nodes, wherein based on a first node of the nodes having transmission paused by flow control, the perform packet transmit arbitration among nodes comprises retain relative priority of a packet departure time for the first node with respect to a second packet departure time associated with a second node of the nodes during a duration of flow control. In some examples, retaining relative priority of a packet departure time for the first node with respect to a second packet departure time associated with a second node of the nodes during a duration of flow control comprises adjust the packet departure time and the second packet departure time to stay within a time window but not rollover.

公开(公告)号：US20190158429A1

公开(公告)日：2019-05-23

申请号：US16260785

申请日：2019-01-29

Applicant: Intel Corporation

Inventor： Ben-Zion FRIEDMAN ,  Noam ELATI ,  Sarig LIVNE

IPC: H04L12/937 ,  H04L12/861 ,  H04L12/879 ,  H04L12/24

Abstract: Techniques to use descriptors for packet transmit scheduling include grouping a plurality of data descriptors associated with blocks of data with a single descriptor. The single descriptor to include information related to the plurality of data descriptors. The single descriptor to be used to schedule transmission of the blocks of data from a computing platform.

公开(公告)号：US20230019974A1

公开(公告)日：2023-01-19

申请号：US17957719

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Srinivasan S. IYENGAR ,  Erik MCSHANE ,  Edward HO ,  Noam ELATI

IPC: G06F1/324 ,  H04L49/1546

Abstract: A network device can place some or all of the packet processing pipeline into a low-power state for detected idle intervals of sufficient duration. The network device detects idleness greater than a critical duration and automatically engages a low-power mode involving clock throttling and/or clock gating. The power savings in the packet processing pipeline in the network device is based on the average long-term residency in idleness. The idle power is reduced for the packet processing pipeline in the network device by detecting average long-term idleness as a function of the minimum latency of the packet processing pipeline, which is used to reduce the clock rate of the packet processing pipeline, thereby resulting in power savings for the network device.

公开(公告)号：US20220141133A1

公开(公告)日：2022-05-05

申请号：US17648196

申请日：2022-01-18

Applicant: Intel Corporation

Inventor： Eliel LOUZOUN ,  Manasi DEVAL ,  Stephen DOYLE ,  Noam ELATI ,  Patrick FLEMING ,  Gregory BOWERS

IPC: H04L45/74 ,  H04L49/90 ,  H04L47/36

Abstract: An apparatus, a method, and a computer program for generating data packets according to a transport protocol from an application buffer comprising a plurality of data streams is provided. The apparatus comprises an input circuit configured to receive metadata comprising at least one of information about data packet types supported by the transport protocol, information about an offset and a length of the supported data packet types, and information about possible stream header start positions, possible payload start positions and possible offsets in the data streams. Further, the apparatus comprises a parsing circuit configured to identify offsets in an application buffer as possible segmentation points based on the metadata, to segment the application buffer at the possible segmentation points into segments for data packets, and to generate data packets according to the transport protocol based on the segments. Furthermore, an apparatus, a method and a computer program for processing the application buffer is provided.

公开(公告)号：US20220086226A1

公开(公告)日：2022-03-17

申请号：US17483458

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Anjali Singhai JAIN ,  Noam ELATI ,  Eliel LOUZOUN ,  Daniel DALY

IPC: H04L67/1097 ,  G06F9/455 ,  G06F13/28

Abstract: Examples described herein relate to a network interface device comprising: a device interface; at least one processor; a direct memory access (DMA) device; and a packet processing circuitry. In some examples, the at least one processor, when operational, is configured to: in connection with a first operation: perform a format translation of a first descriptor from a first format associated with an emulated device to a second format associated with the packet processing circuitry and provide, to the packet processing circuitry, the translated first descriptor. In some examples, the at least one processor, when operational, is configured to: in connection with a second operation: perform a descriptor format translation of a second descriptor from the second format associated with the packet processing circuitry to the first format associated with the emulated software device and provide, to the emulated device, the translated second descriptor.

公开(公告)号：US20210328945A1

公开(公告)日：2021-10-21

申请号：US17359542

申请日：2021-06-26

Applicant: Intel Corporation

Inventor： Noam ELATI ,  Boris KLEIMAN ,  Piotr UMINSKI

IPC: H04L12/861 ,  H04L12/879

Abstract: Examples described herein relate to a network interface device comprising circuitry to: allocate a first number of buffers to store received packets associated with a first descriptor ring; allocate a second number of buffers to store received packets associated with a second descriptor ring; and based on receipt of a packet, copy the received packet into a number of buffers based on whether the received packet is associated with the first descriptor ring or the second descriptor ring. In some examples, the circuitry is to copy the received packet starting at an offset from a start of a starting buffer in a number of buffers, wherein the offset is based on whether the received packet is associated with the first descriptor ring or the second descriptor ring and wherein the number of buffers is based on whether the received packet is associated with the first descriptor ring or the second descriptor ring.

公开(公告)号：US20200210359A1

公开(公告)日：2020-07-02

申请号：US16814710

申请日：2020-03-10

Applicant: Intel Corporation

Inventor： Linden CORNETT ,  Eliel LOUZOUN ,  Anjali Singhai JAIN ,  Ronen Aharon HYATT ,  Danny VOLKIND ,  Noam ELATI ,  Nadav TURBOVICH

IPC: G06F13/24 ,  G06F9/48 ,  G06F13/42

Abstract: Examples described herein relate to a device indicating a number of available interrupt messages that is more than physical resources available to store the available interrupt messages and allocating one or more physical resources to provide one or more interrupt messages based on allocation of the one or more interrupt messages to a destination entity. The destination entity can request a maximum permitted allocation of interrupt messages regardless of interrupt message use level. The destination entity can request a maximum permitted allocation of interrupt messages regardless of interrupt message use level and allocate the requested maximum permitted allocation of interrupt messages for use in a configuration region of a device. However, based on unavailability of a physical resource to store a first interrupt message, allocation of the first interrupt message to a destination entity may not be permitted.