ANALOG-TO-DIGITAL CONVERTER, RECEIVER, BASE STATION, MOBILE DEVICE AND METHOD FOR A TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTER

    公开(公告)号:US20240097693A1

    公开(公告)日:2024-03-21

    申请号:US17933512

    申请日:2022-09-20

    CPC classification number: H03M1/1014 H04B1/40

    Abstract: An analog-to-digital converter, ADC, is provided. The ADC comprises multiple time-interleaved sub-ADCs, a detection circuit, and a calibration circuit. The sub-ADCs are configured to, when the ADC is in a calibration mode, generate a first signal by sampling a calibration signal based on a first clock signal and at least a second clock signal. The first clock signal comprises a phase shift relative to the second clock signal. The calibration circuit is configured to determine a first mismatch between the phase shift and a phase shift threshold based on the first signal. The detection circuit is configured to, when the ADC is in an operation mode, generate a second signal by sampling one of a biased signal to be received by the sub-ADCs or a second calibration signal based on at least one of the first clock signal and the second clock signal. The calibration circuit is configured to determine a second mismatch between the phase shift and the phase shift threshold based on the second signal and calibrate the ADC based on the first and the second mismatch.

    IN-MEMORY ANALOG CHANNEL EQUALIZATION
    4.
    发明公开

    公开(公告)号:US20240113698A1

    公开(公告)日:2024-04-04

    申请号:US17956844

    申请日:2022-09-30

    CPC classification number: H03H17/02 H03H2218/10

    Abstract: A radiofrequency frontend device includes a memory array, which includes a plurality of input lines; a plurality of output lines; and a plurality of impedance devices, each impedance device connecting an input line of the plurality of input lines to an output line of the plurality of output lines, wherein each impedance represents a filter coefficient; wherein the radiofrequency frontend device is configured to provide at each input line of the plurality of input lines a sampled voltage of an analog electric signal, each sampled voltage corresponding to a voltage of the analog electric signal during a respective time period of a plurality of time periods; and when the memory array receives the sampled voltages, the memory array is configured to modify each of the sampled voltages by a respective impedance device of the plurality of impedance devices and sum the modified sampled voltages.

    CLOSED-LOOP BAUD RATE CARRIER AND CARRIER FREQUENCY TUNING FOR WIRELESS CHIP-TO-CHIP INTERFACE

    公开(公告)号:US20220200750A1

    公开(公告)日:2022-06-23

    申请号:US17124536

    申请日:2020-12-17

    Abstract: Various aspects of this disclosure provide a receiver. The receiver may include a down-converter configured to down-convert a received communication signal at a predefined carrier frequency, with a reference signal received from a reference signal generator, and a processor configured to perform a signal quality detection to identify a signal quality metric of the received communication signal at the predefined carrier frequency, and to provide a frequency adjusting signal to the reference signal generator to change the frequency of the reference signal based on the performed signal quality detection to identify the signal quality metric of the received communication signal at the predefined carrier frequency.

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