公开(公告)号：US20230033086A1

公开(公告)日：2023-02-02

申请号：US17791175

申请日：2020-02-07

Applicant: Intel Corporation

Inventor： Chen WANG ,  Dipanjan BASU ,  Richard FASTOW ,  Dimitri KIOUSSIS ,  Yi LI ,  Ebony Lynn MAYS ,  Dimitrios PAVLOPOULOS ,  Junyen TEWG

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/1157 ,  G11C8/14

Abstract: A memory array including a varying width channel is disclosed. The array includes a plurality of WLs, which are above a layer, where the layer can be, for example, a Select Gate Source (SGS) of the memory array, or an isolation layer to isolate a first deck of the array from a second deck of the array. The channel extends through the plurality of word lines and at least partially through the layer. In an example, the channel comprises a first region and a second region. The first region of the channel has a first width that is at least 1 nm different from a second width of the second region of the channel. In an example, the first region extends through the plurality of word lines, and the second region extends through at least a part of the layer underneath the plurality of word lines. In one case, the first width is at least 1 nm less than a second width of the second region of the channel.

公开(公告)号：US20220359441A1

公开(公告)日：2022-11-10

申请号：US17314979

申请日：2021-05-07

Applicant: Intel Corporation

Inventor： Khaled HASNAT ,  Prashant MAJHI ,  Owen JUNGROTH ,  Richard FASTOW ,  Krishna K. PARAT

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

Abstract: Three-dimensional (3D) NAND components formed with control circuitry split across two wafers can provide for more area for control circuitry for an array, enabling improved 3D NAND system performance. In one example, a 3D NAND component includes a first die including a three-dimensional (3D) NAND array and first complementary metal oxide semiconductor (CMOS) control circuitry to access the 3D NAND array, and a second die vertically stacked and bonded with the first die, the second die including second CMOS control circuitry to access the 3D NAND array of the first die.

公开(公告)号：US20200342946A1

公开(公告)日：2020-10-29

申请号：US16396478

申请日：2019-04-26

Applicant: Intel Corporation

Inventor： Han ZHAO ,  Richard FASTOW ,  Krishna K. PARAT ,  Arun THATHACHARY ,  Narayanan RAMANAN

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/08

Abstract: A technique for read or program verify (PV) operations for non-volatile memory is described. In one example, at the end of a program verify operation (e.g., during a program verify recovery phase), a number of wordlines near a selected wordline are ramped down one at a time. Ramping down wordlines near the selected wordline one at a time can significantly reduce the trapped charge in the channel, enabling lower program disturb rates and improved threshold voltage distributions. In one example, the same technique of ramping down wordlines near the selected wordline can be applied to a read operation.

公开(公告)号：US20210096634A1

公开(公告)日：2021-04-01

申请号：US16586957

申请日：2019-09-28

Applicant: Intel Corporation

Inventor： Richard FASTOW ,  Shankar NATARAJAN ,  Chang Wan HA ,  Chee LAW ,  Khaled HASNAT ,  Chuan LIN ,  Shafqat AHMED

IPC: G06F1/3234 ,  G11C16/04 ,  G11C16/30 ,  G11C16/32 ,  G11C16/34

Abstract: A nonvolatile memory supports a standby state where the memory is ready to receive an access command to execute, and a deep power down state where the memory ignores all access commands. The memory can transition from the standby state to the deep power down state in response to a threshold amount of time in the standby state. Thus, the memory can enter the standby state after a command and then transition to the deep power down state after the threshold time.

公开(公告)号：US20190043836A1

公开(公告)日：2019-02-07

申请号：US16011139

申请日：2018-06-18

Applicant: Intel Corporation

Inventor： Richard FASTOW ,  Khaled HASNAT ,  Prashant MAJHI ,  Owen JUNGROTH

IPC: H01L25/065 ,  G11C16/04 ,  G11C16/08 ,  H01L27/11548 ,  H01L27/11575 ,  H01L27/11556 ,  H01L27/11582 ,  H01L23/00

Abstract: Wafer-to-wafer bonding is used to form three-dimensional (3D) memory components such as 3D NAND flash memory with shared control circuitry on one die to access arrays on multiple dies. In one example, a non-volatile storage device includes a first die including a 3D array of non-volatile storage cells and CMOS (complementary metal oxide semiconductor) circuitry. A second die including a second 3D array of non-volatile storage cells is vertically stacked and bonded with the first die. At least a portion of the CMOS circuitry of the first die to access both the first 3D array of non-volatile storage cells of the first die and the second 3D array of non-volatile storage cells of the second die.