公开(公告)号：US20190096452A1

公开(公告)日：2019-03-28

申请号：US15926837

申请日：2018-03-20

Applicant: Intel Corporation

Inventor： Robert A. Branch ,  Murugasamy K. Nachimuthu ,  Sundar Muthusamy

IPC: G11C7/10 ,  G06F13/16 ,  G06F9/4401 ,  G11C14/00 ,  G06F12/10

CPC classification number: G11C7/1072 ,  G06F9/4401 ,  G06F12/10 ,  G06F13/16 ,  G06F13/1694 ,  G06F2212/1044 ,  G11C14/0063 ,  G11C14/0081 ,  G11C14/009

Abstract: Technology for a system is described. The system can include one or more processors. The system can include a memory associated with the one or more processors. The system can include a memory controller comprising logic to create a reserved memory region in a system physical address (SPA) map. The memory controller can comprise logic to detect when the one or more processors are brought online. The memory controller can comprise logic to map the memory associated with the one or more processors that are brought online to the reserved memory region in the SPA map.

公开(公告)号：US20230195616A1

公开(公告)日：2023-06-22

申请号：US17553458

申请日：2021-12-16

Applicant: Intel Corporation

Inventor： Monam Agarwal ,  Anand K. Enamandram ,  Wei Chen ,  Kerry Vander Kamp ,  Robert A. Branch ,  Yen-Cheng Liu

IPC: G06F13/16 ,  G06F12/02

CPC classification number: G06F13/161 ,  G06F12/0238 ,  G06F12/0292 ,  G06F13/1642 ,  G06F13/1668 ,  G06F2212/1021

Abstract: Techniques and mechanisms for identifying a memory access resource which is to be a target of an access request. In an embodiment, a processor comprises route tables which are to provide entries corresponding to different respective memory access resources which are coupled to the processor. The processor further comprises a list of items which each correspond to a different respective range of addresses, wherein the items each include an identifier of a respective route table, and an identifier of a respective index offset. Based on an address of the access request, a decoder circuit of the processor searches the list to identify a corresponding one of the items. In another embodiment, the decoder circuit accesses a route table entry, based on the search, to determine how the access request is to be directed to a particular memory access resource.

公开(公告)号：US20220114115A1

公开(公告)日：2022-04-14

申请号：US17557963

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Anand K. Enamandram ,  Rita Deepak Gupta ,  Robert A. Branch ,  Kerry Vander Kamp

IPC: G06F13/16

Abstract: An apparatus comprising a first memory interface of a first type to couple to at least one first memory device; a second memory interface of a second type to couple to at least one second memory device; and circuitry to interleave memory requests targeting contiguous memory addresses among the at least one first memory device and the at least one second memory device.

公开(公告)号：US11954047B2

公开(公告)日：2024-04-09

申请号：US17033745

申请日：2020-09-26

Applicant: Intel Corporation

Inventor： Mahesh Natu ,  Anand K. Enamandram ,  Manjula Peddireddy ,  Robert A. Branch ,  Tiffany J. Kasanicky ,  Siddhartha Chhabra ,  Hormuzd Khosravi

IPC: G06F12/14 ,  G06F9/30 ,  G06F12/02

CPC classification number: G06F12/1441 ,  G06F9/30101 ,  G06F9/30145 ,  G06F12/0238 ,  G06F12/1408

Abstract: Systems, methods, and apparatuses to implement spatially unique and location independent persistent memory encryption are described. In one embodiment, a system on a chip (SoC) includes at least one persistent range register to indicate a persistent range of memory, an address modifying circuit to check if an address for a memory store request is within the persistent range indicated by the at least one persistent range register, and append a unique identifier value, for a component corresponding to the memory store request for the address, to the address to generate a modified address and output the modified address as an output address when the address is within the persistent range, and output the address as the output address when the address is not within the persistent range, and an encryption engine circuit to generate a ciphertext based on the output address.

公开(公告)号：US11860670B2

公开(公告)日：2024-01-02

申请号：US17553458

申请日：2021-12-16

Applicant: Intel Corporation

Inventor： Monam Agarwal ,  Anand K. Enamandram ,  Wei Chen ,  Kerry Vander Kamp ,  Robert A. Branch ,  Yen-Cheng Liu

IPC: G06F12/02 ,  G06F13/16

CPC classification number: G06F12/0292 ,  G06F12/0238 ,  G06F13/161 ,  G06F13/1642 ,  G06F13/1668 ,  G06F2212/1021

Abstract: Techniques and mechanisms for identifying a memory access resource which is to be a target of an access request. In an embodiment, a processor comprises route tables which are to provide entries corresponding to different respective memory access resources which are coupled to the processor. The processor further comprises a list of items which each correspond to a different respective range of addresses, wherein the items each include an identifier of a respective route table, and an identifier of a respective index offset. Based on an address of the access request, a decoder circuit of the processor searches the list to identify a corresponding one of the items. In another embodiment, the decoder circuit accesses a route table entry, based on the search, to determine how the access request is to be directed to a particular memory access resource.

公开(公告)号：US10515674B2

公开(公告)日：2019-12-24

申请号：US15926837

申请日：2018-03-20

Applicant: Intel Corporation

Inventor： Robert A. Branch ,  Murugasamy K. Nachimuthu ,  Sundar Muthusamy

IPC: G06F12/00 ,  G11C7/10 ,  G06F13/16 ,  G06F9/4401 ,  G11C14/00 ,  G06F12/10 ,  G06F13/00 ,  G06F13/28

Abstract: Technology for a system is described. The system can include one or more processors. The system can include a memory associated with the one or more processors. The system can include a memory controller comprising logic to create a reserved memory region in a system physical address (SPA) map. The memory controller can comprise logic to detect when the one or more processors are brought online. The memory controller can comprise logic to map the memory associated with the one or more processors that are brought online to the reserved memory region in the SPA map.

公开(公告)号：US09922689B2

公开(公告)日：2018-03-20

申请号：US15089370

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Robert A. Branch ,  Murugasamy K. Nachimuthu ,  Sundar Muthusamy

IPC: G06F13/00 ,  G06F13/28 ,  G11C7/10 ,  G06F9/44 ,  G11C14/00 ,  G06F12/10

CPC classification number: G11C7/1072 ,  G06F9/4401 ,  G06F12/10 ,  G06F13/16 ,  G06F13/1694 ,  G06F2212/1044 ,  G11C14/0063 ,  G11C14/0081 ,  G11C14/009

Abstract: Technology for a system is described. The system can include one or more processors. The system can include a memory associated with the one or more processors. The system can include a memory controller comprising logic to create a reserved memory region in a system physical address (SPA) map. The memory controller can comprise logic to detect when the one or more processors are brought online. The memory controller can comprise logic to map the memory associated with the one or more processors that are brought online to the reserved memory region in the SPA map.

公开(公告)号：US20170287532A1

公开(公告)日：2017-10-05

申请号：US15089370

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Robert A. Branch ,  Murugasamy K. Nachimuthu ,  Sundar Muthusamy

IPC: G11C7/10 ,  G11C14/00 ,  G06F9/44

CPC classification number: G11C7/1072 ,  G06F9/4401 ,  G06F12/10 ,  G06F13/16 ,  G06F13/1694 ,  G06F2212/1044 ,  G11C14/0063 ,  G11C14/0081 ,  G11C14/009

Abstract: Technology for a system is described. The system can include one or more processors. The system can include a memory associated with the one or more processors. The system can include a memory controller comprising logic to create a reserved memory region in a system physical address (SPA) map. The memory controller can comprise logic to detect when the one or more processors are brought online. The memory controller can comprise logic to map the memory associated with the one or more processors that are brought online to the reserved memory region in the SPA map.