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    Circuits And Methods For Correcting Errors In Memory
    1.
    发明申请
    Circuits And Methods For Correcting Errors In Memory 有权

    公开(公告)号：US20220075688A1

    公开(公告)日：2022-03-10

    申请号：US17525917

    申请日：2021-11-14

    Applicant: Intel Corporation

    Inventor： Krishna Nagar ,  Brandon Gordon ,  Yi Peng

    IPC: G06F11/10 ,  G06F3/06

    Abstract: An electronic system includes a processor circuit, a memory circuit, and an error correction circuit. The error correction circuit receives information read from the memory circuit. The error correction circuit detects if the information contains an error. The error correction circuit corrects the error in the information to generate corrected information and provides the corrected information and an error signal to the processor circuit. The processor circuit provides the corrected information and a write command to the memory circuit based on the error signal indicating the error. The memory circuit overwrites the information stored in the memory circuit with the corrected information in response to the write command.

    Sharing a JTAG interface among multiple partitions
    3.
    发明授权
    Sharing a JTAG interface among multiple partitions 有权

    公开(公告)号：US10101387B1

    公开(公告)日：2018-10-16

    申请号：US15429008

    申请日：2017-02-09

    Applicant: Intel Corporation

    Inventor： Mahesh A. Iyer ,  Yi Peng

    IPC: G01R31/28 ,  G01R31/317 ,  G01R31/3177

    Abstract: An integrated circuit device includes a first partition and a second partition. The integrated circuit device also includes a Joint Test Action Group (JTAG) system that controls at least a portion of the integrated circuit device via multiple logic signals. The JTAG system includes a JTAG interface receives the multiple logic signals. The JTAG system also includes a JTAG hub instantiated in the first partition and being communicatively coupled to the JTAG interface. The JTAG system further includes JTAG-based logic instantiated in the second partition. The integrated circuit device further includes an interface instantiated in the first partition configured to communicatively couple the JTAG hub to the JTAG-based logic.

    Techniques For Capturing Signals From Logic Circuits At A Logic Analyzer
    4.
    发明公开
    Techniques For Capturing Signals From Logic Circuits At A Logic Analyzer 审中-公开

    公开(公告)号：US20230213581A1

    公开(公告)日：2023-07-06

    申请号：US18122238

    申请日：2023-03-16

    Applicant: Intel Corporation

    Inventor： Yi Peng ,  Nishant Bhargava ,  Velayutham Durairaj

    IPC: G01R31/3177 ,  G06F30/343

    CPC classification number: G01R31/3177 ,  G06F30/343

    Abstract: An integrated circuit includes logic circuits, a logic analyzer circuit, and a multiplexer circuit configurable to provide a value of a signal selected from one of the logic circuits to the logic analyzer circuit. The logic analyzer circuit is configured to store the value of the signal selected by the multiplexer circuit. A method is provided for capturing signals within an integrated circuit. The method includes providing a first logic signal from a first logic circuit to a multiplexer circuit, providing a second logic signal from a second logic circuit to the multiplexer circuit, selecting one of the first logic signal or the second logic signal as a selected signal using the multiplexer circuit, and storing a value of the selected signal in the logic analyzer circuit in the integrated circuit.

    Non-destructive readback and writeback for integrated circuit device
    6.
    发明授权
    Non-destructive readback and writeback for integrated circuit device 有权

    公开(公告)号：US12086460B2

    公开(公告)日：2024-09-10

    申请号：US17132672

    申请日：2020-12-23

    Applicant: Intel Corporation

    Inventor： Bee Yee Ng ,  Jun Pin Tan ,  Yi Peng

    IPC: G06F3/06 ,  G06F1/06 ,  G06F30/343

    CPC classification number: G06F3/0659 ,  G06F1/06 ,  G06F3/0616 ,  G06F3/0673 ,  G06F30/343

    Abstract: Systems and methods for non-destructive readback and writeback of an integrated circuit system are provided. Such a system may include an adaptive logic element including a first register pair. The first register pair may include a first register operating at a first frequency and a second register operating at a second frequency. The second frequency may be equal to or lower than the first frequency. The second register may store data from the first register. The adaptive logic element may also include a first clock providing a first clock signal to the first register and a second clock providing a second clock signal. The adaptive logic element may also include a multiplexer that may select the first clock signal or the second clock signal as a clock source for the second register.

    Circuits And Methods For Accessing Signals In Integrated Circuits
    8.
    发明申请
    Circuits And Methods For Accessing Signals In Integrated Circuits 有权

    公开(公告)号：US20220077856A1

    公开(公告)日：2022-03-10

    申请号：US17525894

    申请日：2021-11-13

    Applicant: Intel Corporation

    Inventor： Yi Peng ,  Brandon Gordon ,  Mahesh A. Iyer ,  Krishna Nagar

    IPC: H03K19/177 ,  G06F30/343

    Abstract: An integrated circuit includes a monitored circuit and a signal analyzer circuit. The signal analyzer circuit includes a logic circuit that determines if a condition signal satisfies a condition to generate an output signal. A first-in-first-out (FIFO) buffer circuit stores opportunistic data indicated by a monitored signal received from the monitored circuit in response to the output signal indicating if the condition signal satisfies the condition. A communication channel transmits the opportunistic data stored in the FIFO buffer circuit outside the integrated circuit.

    CIRCUIT DESIGN VISIBILITY IN INTEGRATED CIRCUIT DEVICES
    9.
    发明申请
    CIRCUIT DESIGN VISIBILITY IN INTEGRATED CIRCUIT DEVICES 有权

    公开(公告)号：US20210012051A1

    公开(公告)日：2021-01-14

    申请号：US17033208

    申请日：2020-09-25

    Applicant: Intel Corporation

    Inventor： Yi Peng ,  Brandon Lewis Gordon

    IPC: G06F30/343 ,  G06F30/331

    Abstract: A system includes an integrated circuit device configured to implement a circuit design. The integrated circuit device includes a communication interface configured to receive the circuit design in a configuration bitstream and instrumentation logic in the configuration bitstream and signal collector block configured to collect signal data based on the instrumentation logic during implementation of the circuit design.

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