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公开(公告)号：US11950407B2
公开(公告)日：2024-04-02
申请号：US16828507
申请日：2020-03-24
Applicant: Intel Corporation
Inventor： Juan G. Alzate Vinasco , Travis W. Lajoie , Abhishek A. Sharma , Kimberly L Pierce , Elliot N. Tan , Yu-Jin Chen , Van H. Le , Pei-Hua Wang , Bernhard Sell
IPC: H10B12/00 , H01L23/522 , H01L23/528 , H01L49/02
CPC classification number: H10B12/315 , H01L23/5226 , H01L23/528 , H01L28/91 , H10B12/0335 , H10B12/05 , H10B12/318 , H10B12/482 , H10B12/485
Abstract: Embodiments herein describe techniques for a memory device including at least two memory cells. A first memory cell includes a first storage cell and a first transistor to control access to the first storage cell. A second memory cell includes a second storage cell and a second transistor to control access to the second storage cell. A shared contact electrode is shared between the first transistor and the second transistor, the shared contact electrode being coupled to a source area or a drain area of the first transistor, coupled to a source area or a drain area of the second transistor, and further being coupled to a bit line of the memory device. Other embodiments may be described and/or claimed.
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公开(公告)号：US20230102219A1
公开(公告)日：2023-03-30
申请号：US17478720
申请日：2021-09-17
Applicant: Intel Corporation
Inventor： Arnab Sen Gupta , Matthew V. Metz , Hui Jae Yoo , Justin R. Weber , Van H. Le , Jason C. Retasket , Abhishek A. Sharma , Noriyuki Sato , Yu-Jin Chen , Eric Mattson , Edward O. Johnson, JR.
IPC: H01L29/45 , H01L29/786 , H01L29/78 , H01L29/66 , H01L27/108 , H01L29/417
Abstract: Described herein are integrated circuit devices with metal-oxide semiconductor channels and carbon source and drain (S/D) contacts. S/D contacts conduct current to and from the semiconductor devices, e.g., to the source and drain regions of a transistor. Carbon S/D contacts may be particularly useful with semiconductor devices that use certain channel materials, such as indium gallium zinc oxide.
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公开(公告)号：US11063088B2
公开(公告)日：2021-07-13
申请号：US16706470
申请日：2019-12-06
Applicant: Intel Corporation
Inventor： Daniel Ouellette , Christopher Wiegand , Justin Brockman , Tofizur Rahman , Oleg Golonzka , Angeline Smith , Andrew Smith , James Pellegren , Aaron Littlejohn , Juan G. Alzate-Vinasco , Yu-Jin Chen , Tanmoy Pramanik
Abstract: A memory device includes a first electrode, a second electrode and a magnetic tunnel junction (MTJ) between the first electrode and the second electrode. The MTJ includes a fixed magnet, a free magnet and a tunnel barrier between the fixed magnet and the free magnet. The MTJ further includes a conductive layer between the free magnet and the second electrode, the conductive layer having a metallic dopant, where the metallic dopant has a concentration that increase with distance from an interface between the free magnet and the conductive layer. A capping layer is between the conductive layer and the second electrode.
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公开(公告)号：US20210175284A1
公开(公告)日：2021-06-10
申请号：US16706470
申请日：2019-12-06
Applicant: Intel Corporation
Inventor： Daniel Ouellette , Christopher Wiegand , Justin Brockman , Tofizur Rahman , Oleg Golonzka , Angeline Smith , Andrew Smith , James Pellegren , Aaron Littlejohn , Juan G. Alzate-Vinasco , Yu-Jin Chen , Tanmoy Pramanik
Abstract: A memory device includes a first electrode, a second electrode and a magnetic tunnel junction (MTJ) between the first electrode and the second electrode. The MTJ includes a fixed magnet, a free magnet and a tunnel barrier between the fixed magnet and the free magnet. The MTJ further includes a conductive layer between the free magnet and the second electrode, the conductive layer having a metallic dopant, where the metallic dopant has a concentration that increase with distance from an interface between the free magnet and the conductive layer. A capping layer is between the conductive layer and the second electrode.
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