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    MEMS-CMOS DEVICE THAT MINIMIZES OUTGASSING AND METHODS OF MANUFACTURE
    1.
    发明申请
    MEMS-CMOS DEVICE THAT MINIMIZES OUTGASSING AND METHODS OF MANUFACTURE 有权
    最小化出口的MEMS-CMOS器件和制造方法

    公开(公告)号：US20170073217A1

    公开(公告)日：2017-03-16

    申请号：US15366495

    申请日：2016-12-01

    Applicant: INVENSENSE, INC.

    Inventor： Peter SMEYS ,  Jong Il SHIN ,  Jongwoo SHIN

    IPC: B81B7/00 ,  B81C1/00

    CPC classification number: B81B7/0041 ,  B81B2207/012 ,  B81B2207/094 ,  B81C1/00293 ,  B81C2201/013 ,  B81C2201/0133 ,  B81C2201/016 ,  B81C2203/035 ,  B81C2203/0792

    Abstract: A MEMS device is disclosed. The MEMS device includes a first substrate. At least one structure is formed within the first substrate. The first substrate includes at least one first conductive pad thereon. The MEMS device also includes a second substrate. The second substrate includes a passivation layer. The passivation layer includes a plurality of layers. A top layer of the plurality of layers comprises an outgassing barrier layer. At least one second conductive pad and at least one electrode are coupled to the top layer. At least one first conductive pad is coupled to the at least one second conductive pad.

    Abstract translation: 公开了MEMS器件。 MEMS器件包括第一衬底。 在第一基板内形成至少一个结构。 第一衬底包括至少一个第一导电焊盘。 MEMS器件还包括第二衬底。 第二基板包括钝化层。 钝化层包括多个层。 多个层的顶层包括除气阻挡层。 至少一个第二导电焊盘和至少一个电极耦合到顶层。 至少一个第一导电焊盘耦合到所述至少一个第二导电焊盘。

    MEMS GAP CONTROL STRUCTURES
    2.
    发明申请
    MEMS GAP CONTROL STRUCTURES 审中-公开

    公开(公告)号：US20190241432A1

    公开(公告)日：2019-08-08

    申请号：US16389472

    申请日：2019-04-19

    Applicant: InvenSense, Inc.

    Inventor： Jong Il SHIN ,  Peter SMEYS ,  Bongsang KIM

    IPC: B81C1/00 ,  B81B3/00

    Abstract: Provided herein is an apparatus including a cavity in a first side of a first silicon wafer, and an oxide layer on the first side and in the cavity. A first side of a second silicon wafer is bonded to the first side of the first silicon wafer. A gap control structure is on a second side of the second silicon wafer, and a MEMS structure in the second silicon wafer. A eutectic bond is bonding the second side of the second silicon wafer to a third silicon wafer. A lower cavity is between the second side of the silicon wafer and the third silicon wafer, wherein the gap control structure is outside of the lower cavity and the eutectic bond.

    CMOS-MEMS INTEGRATION USING METAL SILICIDE FORMATION
    4.
    发明申请
    CMOS-MEMS INTEGRATION USING METAL SILICIDE FORMATION 有权
    使用金属硅化物形成的CMOS-MEMS集成

    公开(公告)号：US20170057813A1

    公开(公告)日：2017-03-02

    申请号：US14838237

    申请日：2015-08-27

    Applicant: InvenSense, Inc.

    Inventor： Jong Il SHIN ,  Peter SMEYS ,  Jongwoo SHIN

    IPC: B81C1/00 ,  B81B7/00

    CPC classification number: B81C1/00238 ,  B81B7/0006 ,  B81B2207/012 ,  B81C2203/019 ,  B81C2203/036 ,  B81C2203/0792

    Abstract: A method and system for forming a MEMS device are disclosed. In a first aspect, the method comprises providing a conductive material over at least a portion of a top metal layer of a base substrate, patterning the conductive material and the at least a portion of the top metal layer, and bonding the conductive material with a device layer of a MEMS substrate via metal silicide formation. In a second aspect, the MEMS device comprises a MEMS substrate, wherein the MEMS substrate includes a handle layer, a device layer, and an insulating layer in between. The MEMS device further comprises a base substrate, wherein the base substrate includes a top metal layer and a conductive material over at least a portion of the top metal layer, wherein the conductive material is bonded with the device layer via metal silicide formation.

    Abstract translation: 公开了一种用于形成MEMS器件的方法和系统。 在第一方面，该方法包括在基底衬底的顶部金属层的至少一部分上提供导电材料，图案化导电材料和顶部金属层的至少一部分，以及将导电材料与 通过金属硅化物形成MEMS衬底的器件层。 在第二方面，MEMS器件包括MEMS衬底，其中MEMS衬底包括手柄层，器件层和其间的绝缘层。 MEMS器件还包括基底，其中基底衬底包括在顶部金属层的至少一部分上的顶部金属层和导电材料，其中导电材料通过金属硅化物形成与器件层结合。

    CMOS-MEMS INTEGRATED DEVICE INCLUDING MULTIPLE CAVITIES AT DIFFERENT CONTROLLED PRESSURES AND METHODS OF MANUFACTURE
    6.
    发明申请
    CMOS-MEMS INTEGRATED DEVICE INCLUDING MULTIPLE CAVITIES AT DIFFERENT CONTROLLED PRESSURES AND METHODS OF MANUFACTURE 有权
    CMOS-MEMS集成器件，其中包括在不同的控制压力下的多个CAVIITY和制造方法

    公开(公告)号：US20150129991A1

    公开(公告)日：2015-05-14

    申请号：US14603185

    申请日：2015-01-22

    Applicant: InvenSense, Inc.

    Inventor： Daesung LEE ,  Jongwoo SHIN ,  Jong Il SHIN ,  Peter SMEYS ,  Martin LIM

    IPC: B81C1/00 ,  B81B7/00

    CPC classification number: B81C1/0023 ,  B81B7/0038 ,  B81B7/0041 ,  B81B7/02 ,  B81B2201/0228 ,  B81B2207/017 ,  B81C1/00285 ,  B81C2203/019 ,  B81C2203/035 ,  B81C2203/0785

    Abstract: An integrated MEMS device comprises two substrates where the first and second substrates are coupled together and have two enclosures there between. One of the first and second substrates includes an outgassing source layer and an outgassing barrier layer to adjust pressure within the two enclosures. The method includes depositing and patterning an outgassing source layer and a first outgassing barrier layer on the substrate, resulting in two cross-sections. In one of the two cross-sections a top surface of the outgassing source layer is not covered by the outgassing barrier layer and in the other of the two cross-sections the outgassing source layer is encapsulated in the outgassing barrier layer. The method also includes depositing conformally a second outgassing barrier layer and etching the second outgassing barrier layer such that a spacer of the second outgassing barrier layer is left on sidewalls of the outgassing source layer.

    Abstract translation: 集成MEMS器件包括两个基板，其中第一和第二基板耦合在一起并且其间具有两个外壳。 第一和第二基板之一包括除气源层和去气阻挡层，以调节两个外壳内的压力。 该方法包括在基板上沉积和图案化除气源层和第一除气阻挡层，产生两个横截面。 在两个横截面之一中，除气源层的顶表面不被除气阻挡层覆盖，而在两个横截面中的另一个中，除气源层被封装在除气阻挡层中。 该方法还包括平行地沉积第二除气阻挡层并蚀刻第二除气阻挡层，使得第二除气阻挡层的间隔物留在除气源层的侧壁上。

    CMOS-MEMS INTEGRATED DEVICE INCLUDING A CONTACT LAYER AND METHODS OF MANUFACTURE
    7.
    发明申请
    CMOS-MEMS INTEGRATED DEVICE INCLUDING A CONTACT LAYER AND METHODS OF MANUFACTURE 有权
    包含接触层的CMOS-MEMS集成器件及其制造方法

    公开(公告)号：US20160362296A1

    公开(公告)日：2016-12-15

    申请号：US14738645

    申请日：2015-06-12

    Applicant: InvenSense, Inc.

    Inventor： Daesung LEE ,  Jongwoo SHIN ,  Jong Il SHIN ,  Peter SMEYS

    IPC: B81C1/00

    CPC classification number: B81C1/00301 ,  B81C2201/013 ,  B81C2203/036 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/5226

    Abstract: A method for forming a MEMS device is disclosed. The MEMS device includes a MEMS substrate and a base substrate. The MEMS substrate, where includes a handle layer, a device layer and an insulating layer in between. The method includes the sequential steps of: providing a standoff on the device layer; etching a via through the device layer and the insulating layer; providing a contact layer within the via, wherein the contact layer provides electrical connection between the device layer and the handle layer; providing a bonding layer on the standoff; and bonding the bonding layer to pads on the base substrate.

    Abstract translation: 公开了一种用于形成MEMS器件的方法。 MEMS器件包括MEMS衬底和基底衬底。 MEMS衬底，其中包括手柄层，器件层和绝缘层。 该方法包括以下顺序步骤：在设备层上提供间隔; 通过器件层和绝缘层蚀刻通孔; 在所述通孔内提供接触层，其中所述接触层在所述器件层和所述手柄层之间提供电连接; 在支架上提供粘合层; 以及将所述结合层粘合到所述基底基板上的焊盘。

    MEMS-CMOS DEVICE THAT MINIMIZES OUTGASSING AND METHODS OF MANUFACTURE
    8.
    发明申请
    MEMS-CMOS DEVICE THAT MINIMIZES OUTGASSING AND METHODS OF MANUFACTURE 有权
    最小化出口的MEMS-CMOS器件和制造方法

    公开(公告)号：US20160221819A1

    公开(公告)日：2016-08-04

    申请号：US14748012

    申请日：2015-06-23

    Applicant: InvenSense, Inc.

    Inventor： Peter SMEYS ,  Jong Il SHIN ,  Jongwoo SHIN

    IPC: B81B7/00 ,  B81C1/00

    CPC classification number: B81B7/0041 ,  B81B2207/012 ,  B81B2207/094 ,  B81C1/00293 ,  B81C2201/013 ,  B81C2201/0133 ,  B81C2201/016 ,  B81C2203/035 ,  B81C2203/0792

    Abstract: A MEMS device is disclosed. The MEMS device includes a first substrate. At least one structure is formed within the first substrate. The first substrate includes at least one first conductive pad thereon. The MEMS device also includes a second substrate. The second substrate includes a passivation layer. The passivation layer includes a plurality of layers. A top layer of the plurality of layers comprises an outgassing barrier layer. At least one second conductive pad and at least one electrode are coupled to the top layer. At least one first conductive pad is coupled to the at least one second conductive pad.

    Abstract translation: 公开了MEMS器件。 MEMS器件包括第一衬底。 在第一基板内形成至少一个结构。 第一衬底包括至少一个第一导电焊盘。 MEMS装置还包括第二基板。 第二基板包括钝化层。 钝化层包括多个层。 多个层的顶层包括除气阻挡层。 至少一个第二导电焊盘和至少一个电极耦合到顶层。 至少一个第一导电焊盘耦合到所述至少一个第二导电焊盘。

    INTERNAL BARRIER FOR ENCLOSED MEMS DEVICES
    9.
    发明申请
    INTERNAL BARRIER FOR ENCLOSED MEMS DEVICES 审中-公开
    用于封装的MEMS器件的内部障碍

    公开(公告)号：US20160075554A1

    公开(公告)日：2016-03-17

    申请号：US14850860

    申请日：2015-09-10

    Applicant: InvenSense, Inc.

    Inventor： Anatole HUANG ,  Jongwoo SHIN ,  Peter SMEYS ,  Cerina ZHANG ,  Jong Il SHIN

    IPC: B81B7/00 ,  B81C1/00

    Abstract: A MEMS device having a channel configured to avoid particle contamination is disclosed. The MEMS device includes a MEMS substrate and a base substrate. The MEMS substrate includes a MEMS device area, a seal ring and a channel. The seal ring provides for dividing the MEMS device area into a plurality of cavities, wherein at least one of the plurality of cavities includes one or more vent holes. The channel is configured between the one or more vent holes and the MEMS device area. Preferably, the channel is configured to minimize particles entering the MEMS device area directly. The base substrate is coupled to the MEMS device substrate.

    Abstract translation: 公开了具有被配置为避免颗粒污染的通道的MEMS器件。 MEMS器件包括MEMS衬底和基底衬底。 MEMS衬底包括MEMS器件区域，密封环和沟道。 密封环提供将MEMS器件区域分成多个空腔，其中多个空腔中的至少一个包括一个或多个通气孔。 通道配置在一个或多个通气孔和MEMS器件区域之间。 优选地，通道被配置为使直接进入MEMS器件区域的颗粒最小化。 基底衬底耦合到MEMS器件衬底。

    CMOS-MEMS INTEGRATION BY SEQUENTIAL BONDING METHOD
    10.
    发明申请
    CMOS-MEMS INTEGRATION BY SEQUENTIAL BONDING METHOD 有权
    CMOS-MEMS集成通过顺序连接方法

    公开(公告)号：US20150311178A1

    公开(公告)日：2015-10-29

    申请号：US14696994

    申请日：2015-04-27

    Applicant: InvenSense, Inc.

    Inventor： Jong Il SHIN ,  Peter SMEYS ,  Jongwoo SHIN

    IPC: H01L23/00

    CPC classification number: H01L24/83 ,  B81B2207/012 ,  B81C1/00238 ,  B81C2203/019 ,  B81C2203/035 ,  B81C2203/0792 ,  H01L2224/83065 ,  H01L2224/83805 ,  H01L2224/83951

    Abstract: Methods for bonding two wafers are disclosed. In one aspect, a first wafer includes an integrated circuit and the second wafer including a MEMS device. The method comprises depositing a bond pad on a metal on the first wafer and sequentially bonding the first wafer to the second wafer utilizing first and second temperatures. The second wafer is bonded to the bond pad at the first temperature and the bond pad and the metal are bonded at the second temperature. In another aspect, a first wafer including an integrated circuit, the second wafer includes a MEMS device. The method comprises depositing a bond pad on a metal on one of the first wafer and the second wafer and bonding the first wafer to the second wafer at a first temperature via a direct bond interface. The method includes bonding the bond pad to the metal at a second temperature.

    Abstract translation: 公开了粘合两个晶片的方法。 在一个方面，第一晶片包括集成电路，第二晶片包括MEMS器件。 该方法包括在第一晶片上的金属上沉积接合焊盘，并且利用第一和第二温度将第一晶片顺序地结合到第二晶片。 第二晶片在第一温度下接合到接合焊盘，并且接合焊盘和金属在第二温度下结合。 在另一方面，包括集成电路的第一晶片，所述第二晶片包括MEMS器件。 该方法包括在第一晶片和第二晶片之一上的金属上沉积接合焊盘，并且通过直接键合界面在第一温度下将第一晶片接合到第二晶片。 该方法包括在第二温度下将接合焊盘接合到金属。

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