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    CMOS-MEMS INTEGRATED DEVICE INCLUDING A CONTACT LAYER AND METHODS OF MANUFACTURE
    1.
    发明申请
    CMOS-MEMS INTEGRATED DEVICE INCLUDING A CONTACT LAYER AND METHODS OF MANUFACTURE 有权
    包含接触层的CMOS-MEMS集成器件及其制造方法

    公开(公告)号：US20160362296A1

    公开(公告)日：2016-12-15

    申请号：US14738645

    申请日：2015-06-12

    Applicant: InvenSense, Inc.

    Inventor： Daesung LEE ,  Jongwoo SHIN ,  Jong Il SHIN ,  Peter SMEYS

    IPC: B81C1/00

    CPC classification number: B81C1/00301 ,  B81C2201/013 ,  B81C2203/036 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/5226

    Abstract: A method for forming a MEMS device is disclosed. The MEMS device includes a MEMS substrate and a base substrate. The MEMS substrate, where includes a handle layer, a device layer and an insulating layer in between. The method includes the sequential steps of: providing a standoff on the device layer; etching a via through the device layer and the insulating layer; providing a contact layer within the via, wherein the contact layer provides electrical connection between the device layer and the handle layer; providing a bonding layer on the standoff; and bonding the bonding layer to pads on the base substrate.

    Abstract translation: 公开了一种用于形成MEMS器件的方法。 MEMS器件包括MEMS衬底和基底衬底。 MEMS衬底，其中包括手柄层，器件层和绝缘层。 该方法包括以下顺序步骤：在设备层上提供间隔; 通过器件层和绝缘层蚀刻通孔; 在所述通孔内提供接触层，其中所述接触层在所述器件层和所述手柄层之间提供电连接; 在支架上提供粘合层; 以及将所述结合层粘合到所述基底基板上的焊盘。

    CMOS-MEMS INTEGRATED DEVICE WITH SELECTIVE BOND PAD PROTECTION
    2.
    发明申请
    CMOS-MEMS INTEGRATED DEVICE WITH SELECTIVE BOND PAD PROTECTION 有权
    具有选择性焊盘保护的CMOS-MEMS集成器件

    公开(公告)号：US20160318755A1

    公开(公告)日：2016-11-03

    申请号：US14699938

    申请日：2015-04-29

    Applicant: InvenSense, Inc.

    Inventor： Daesung LEE

    IPC: B81C1/00

    CPC classification number: B81C1/00801 ,  B81B7/0025 ,  B81B2207/07 ,  B81C2201/053 ,  B81C2203/0785

    Abstract: A method and system for preparing a semiconductor wafer are disclosed. In a first aspect, the method comprises providing a passivation layer over a patterned top metal on the semiconductor wafer, etching the passivation layer to open a bond pad in the semiconductor wafer using a first mask, depositing a protection layer on the semiconductor wafer, patterning the protective layer using a second mask, and etching the passivation layer to open other electrodes in the semiconductor wafer using a third mask. The system comprises a MEMS device that further comprises a first substrate and a second substrate bonded to the first substrate, wherein the second substrate is prepared by the aforementioned steps of the method.

    Abstract translation: 公开了一种用于制备半导体晶片的方法和系统。 在第一方面，该方法包括在半导体晶片上的图案化的顶部金属上提供钝化层，蚀刻钝化层以使用第一掩模打开半导体晶片中的接合焊盘，在半导体晶片上沉积保护层，图案化 使用第二掩模的保护层，并且使用第三掩模蚀刻钝化层以打开半导体晶片中的其它电极。 该系统包括MEMS器件，其还包括第一基底和与第一基底结合的第二基底，其中第二基底是通过上述方法的步骤制备的。

    CMOS-MEMS INTEGRATED DEVICE WITH SELECTIVE BOND PAD PROTECTION
    3.
    发明申请
    CMOS-MEMS INTEGRATED DEVICE WITH SELECTIVE BOND PAD PROTECTION 审中-公开
    具有选择性焊盘保护的CMOS-MEMS集成器件

    公开(公告)号：US20170066648A1

    公开(公告)日：2017-03-09

    申请号：US15356916

    申请日：2016-11-21

    Applicant: INVENSENSE, INC.

    Inventor： Daesung LEE

    IPC: B81C1/00 ,  B81B7/00

    CPC classification number: B81C1/00801 ,  B81B7/0025 ,  B81B2207/07 ,  B81C2201/053 ,  B81C2203/0785

    Abstract: A method and system for preparing a semiconductor wafer are disclosed. In a first aspect, the method comprises providing a passivation layer over a patterned top metal on the semiconductor wafer, etching the passivation layer to open a bond pad in the semiconductor wafer using a first mask, depositing a protection layer on the semiconductor wafer, patterning the protective layer using a second mask, and etching the passivation layer to open other electrodes in the semiconductor wafer using a third mask. The system comprises a MEMS device that further comprises a first substrate and a second substrate bonded to the first substrate, wherein the second substrate is prepared by the aforementioned steps of the method.

    Abstract translation: 公开了一种用于制备半导体晶片的方法和系统。 在第一方面，该方法包括在半导体晶片上的图案化顶部金属上提供钝化层，蚀刻钝化层以使用第一掩模打开半导体晶片中的接合焊盘，在半导体晶片上沉积保护层，图案化 使用第二掩模的保护层，并且使用第三掩模蚀刻钝化层以打开半导体晶片中的其它电极。 该系统包括MEMS器件，其还包括第一基底和与第一基底结合的第二基底，其中第二基底是通过上述方法的步骤制备的。

    ACTUATOR LAYER PATTERNING WITH TOPOGRAPHY
    4.
    发明申请
    ACTUATOR LAYER PATTERNING WITH TOPOGRAPHY 审中-公开

    公开(公告)号：US20200131031A1

    公开(公告)日：2020-04-30

    申请号：US16440860

    申请日：2019-06-13

    Applicant: InvenSense, Inc.

    Inventor： Daesung LEE ,  Dongyang KANG ,  Chienlu CHANG ,  Bongsang KIM ,  Alan CUTHBERTSON

    IPC: B81B7/02 ,  B81C1/00 ,  B81C3/00

    Abstract: Provided herein is a method including fusion bonding a handle wafer to a first side of a device wafer. A hardmask is deposited on a second side of the device wafer, wherein the second side is planar. The hardmask is etched to form a MEMS device pattern and a standoff pattern. Standoffs are formed on the device wafer, wherein the standoffs are defined by the standoff pattern. A eutectic bond metal is deposited on the standoffs, the device wafer, and the hardmask. A first photoresist is deposited and removed, such that the first photoresist covers the standoffs. The eutectic bond metal is etched using the first photoresist. The MEMS device pattern is etched into the device wafer. The first photoresist and the hardmask are removed.

    CMOS-MEMS INTEGRATED DEVICE WITHOUT STANDOFF IN MEMS
    5.
    发明申请
    CMOS-MEMS INTEGRATED DEVICE WITHOUT STANDOFF IN MEMS 审中-公开

    公开(公告)号：US20190382258A1

    公开(公告)日：2019-12-19

    申请号：US16366672

    申请日：2019-03-27

    Applicant: InvenSense, Inc.

    Inventor： Daesung LEE ,  Jeff Chunchieh HUANG

    IPC: B81B7/00 ,  B81C1/00

    Abstract: An apparatus includes a MEMS wafer with a device layer and a handle substrate bonded to the device layer. The apparatus also includes a CMOS wafer including an oxide layer, and a passivation layer overlying the oxide layer. A bonding electrode overlies the passivation layer and a bump stop electrode overlies the passivation layer. A eutectic bond is between a first bonding metal on the bonding electrode and a second bonding metal on the MEMS wafer. A sensing electrode is positioned adjacent to the bump stop electrode and the bonding electrode. A sensing gap is positioned between the sensing electrode and the device layer, wherein the sensing gap is greater than a bump stop gap positioned between the bump stop electrode and the device layer.

    TWO DIFFERENT CONDUCTIVE BUMP STOPS ON CMOS-MEMS BONDED STRUCTURE
    6.
    发明申请
    TWO DIFFERENT CONDUCTIVE BUMP STOPS ON CMOS-MEMS BONDED STRUCTURE 审中-公开

    公开(公告)号：US20180016135A1

    公开(公告)日：2018-01-18

    申请号：US15645665

    申请日：2017-07-10

    Applicant: InvenSense, Inc.

    Inventor： Daesung LEE ,  Jeff HUANG ,  Ki Young LEE

    IPC: B81C1/00

    CPC classification number: B81C1/00238 ,  B81B7/007 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2207/012 ,  B81C1/00269 ,  B81C1/00301 ,  B81C2203/0109 ,  B81C2203/035 ,  B81C2203/0792

    Abstract: Provided herein is a method including forming a micro-electro-mechanical system (“MEMS”) wafer including a first MEMS device and a second MEMS device. A complementary metal-oxide semiconductor (“CMOS”) wafer is formed including a first electrically conductive via and a second electrically conductive via. A layer stack including a first conductive layer, a second conductive layer, and a bond layer is deposited over the first electrically conductive via and the second electrically conductive via. The layer stack is etched to define a first standoff, a second standoff, a third standoff, a first bump stop over the first electrically conductive via, and a second bump stop over the second electrically conductive via. The first bump stop and the second bump stop are etched to remove the bond layer. The first bump stop is further etched to remove the second conductive layer. The MEMS wafer is bonded to the CMOS wafer.

    CMOS MEMS INTEGRATED DEVICE WITH INCREASED SHIELD VERTICAL GAP
    7.
    发明申请
    CMOS MEMS INTEGRATED DEVICE WITH INCREASED SHIELD VERTICAL GAP 审中-公开

    公开(公告)号：US20190382261A1

    公开(公告)日：2019-12-19

    申请号：US16382102

    申请日：2019-04-11

    Applicant: InvenSense, Inc.

    Inventor： Daesung LEE

    IPC: B81C1/00 ,  B81B7/00 ,  B81B7/02

    Abstract: An apparatus includes a MEMS wafer with a device layer and a handle substrate bonded to the device layer. A complementary metal-oxide semiconductor (“CMOS”) wafer includes an oxide layer, and a passivation layer overlying the oxide layer. A bonding electrode overlies the passivation layer. A eutectic bond is between a first bonding metal on the bonding electrode and a second bonding metal on the MEMS wafer. A sensing electrode overlies the passivation layer. A shield electrode is adjacent to the sensing electrode. A sensing gap is positioned between the sensing electrode and the device layer, wherein the sensing gap is smaller than a shield gap positioned between the shield electrode and the device layer.

    CMOS-MEMS INTEGRATED DEVICE INCLUDING MULTIPLE CAVITIES AT DIFFERENT CONTROLLED PRESSURES AND METHODS OF MANUFACTURE
    9.
    发明申请
    CMOS-MEMS INTEGRATED DEVICE INCLUDING MULTIPLE CAVITIES AT DIFFERENT CONTROLLED PRESSURES AND METHODS OF MANUFACTURE 有权
    CMOS-MEMS集成器件，其中包括在不同的控制压力下的多个CAVIITY和制造方法

    公开(公告)号：US20150129991A1

    公开(公告)日：2015-05-14

    申请号：US14603185

    申请日：2015-01-22

    Applicant: InvenSense, Inc.

    Inventor： Daesung LEE ,  Jongwoo SHIN ,  Jong Il SHIN ,  Peter SMEYS ,  Martin LIM

    IPC: B81C1/00 ,  B81B7/00

    CPC classification number: B81C1/0023 ,  B81B7/0038 ,  B81B7/0041 ,  B81B7/02 ,  B81B2201/0228 ,  B81B2207/017 ,  B81C1/00285 ,  B81C2203/019 ,  B81C2203/035 ,  B81C2203/0785

    Abstract: An integrated MEMS device comprises two substrates where the first and second substrates are coupled together and have two enclosures there between. One of the first and second substrates includes an outgassing source layer and an outgassing barrier layer to adjust pressure within the two enclosures. The method includes depositing and patterning an outgassing source layer and a first outgassing barrier layer on the substrate, resulting in two cross-sections. In one of the two cross-sections a top surface of the outgassing source layer is not covered by the outgassing barrier layer and in the other of the two cross-sections the outgassing source layer is encapsulated in the outgassing barrier layer. The method also includes depositing conformally a second outgassing barrier layer and etching the second outgassing barrier layer such that a spacer of the second outgassing barrier layer is left on sidewalls of the outgassing source layer.

    Abstract translation: 集成MEMS器件包括两个基板，其中第一和第二基板耦合在一起并且其间具有两个外壳。 第一和第二基板之一包括除气源层和去气阻挡层，以调节两个外壳内的压力。 该方法包括在基板上沉积和图案化除气源层和第一除气阻挡层，产生两个横截面。 在两个横截面之一中，除气源层的顶表面不被除气阻挡层覆盖，而在两个横截面中的另一个中，除气源层被封装在除气阻挡层中。 该方法还包括平行地沉积第二除气阻挡层并蚀刻第二除气阻挡层，使得第二除气阻挡层的间隔物留在除气源层的侧壁上。

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