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1.发明申请Catheter assemblies and injection molding processes and equipment for making the same 审中-公开导管组件和注射成型工艺以及制造相同的设备公开(公告)号：US20090143767A1
公开(公告)日：2009-06-04
申请号：US12290448
申请日：2008-10-30
申请人： James Fentress , Scott A. O'Connor , Scott A. White , Lawrence A. Monahan , Frank E. Martin , Kevin G. Tingey , Craig N. Gawreluk
发明人： James Fentress , Scott A. O'Connor , Scott A. White , Lawrence A. Monahan , Frank E. Martin , Kevin G. Tingey , Craig N. Gawreluk
CPC分类号： A61M25/0009 , A61M25/0014 , B29C45/0001 , B29C45/0003 , B29C45/16 , B29C45/261 , B29C45/2708 , B29K2075/00 , B29L2031/7542
摘要： Various single-part catheter assemblies, multi-part integrated catheter assemblies, and methods for making the same are disclosed. The single-part catheter assemblies include a catheter hub integrally formed with a catheter tube for insertion into the bloodstream of a patient. The multi-part integrated catheter assemblies include a catheter hub integrally formed to a catheter tube for insertion into the bloodstream of a patient. The catheter assemblies of the invention may be injection molded in a single step or in multiple steps by injecting flows of molten plastic into a cavity of molds provided herein such that the flows converge into an even distribution about the circumference of the sleeve. The mold may have a core pin designed to fit into the cavity. Through the use of the even distribution of flows, the core pin may be seated within the cavity in an untensioned manner. The catheter assemblies of the invention may be produced of a single material or of multiple materials.
摘要翻译： 公开了各种单一部件导管组件，多部分集成导管组件及其制造方法。 单组件导管组件包括与用于插入患者血流中的导管管一体形成的导管座。 多部分集成导管组件包括与导管管一体形成的用于插入患者血流的导管套管。 本发明的导管组件可以在单个步骤或多个步骤中通过将熔融塑料流注入本文提供的模具的空腔中而注射模制，使得流体围绕套筒的圆周收敛成均匀分布。 模具可以具有设计成适合于空腔的芯销。 通过使用均匀的流动分布，芯销可以以未张紧的方式安置在空腔内。 本发明的导管组件可以由单一材料或多种材料制成。
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公开(公告)号：US07350119B1
公开(公告)日：2008-03-25
申请号：US10859284
申请日：2004-06-02
CPC分类号： G11C29/44 , G06F12/0802 , G11C29/4401 , G11C29/802 , G11C2029/0401
摘要： A hierarchical encoding format for coding repairs to devices within a computing system. A device, such as a cache memory, is logically partitioned into a plurality of sub-portions. Various portions of the sub-portions are identifiable as different levels of hierarchy of the device. A first sub-portion may corresponds to a particular cache, a second sub-portion may correspond to a particular way of the cache, and so on. The encoding format comprises a series of bits with a first portion corresponding to a first level of the hierarchy, and a second portion of the bits corresponds to a second level of the hierarchy. Each of the first and second portions of bits are preceded by a different valued bit which serves to identify the hierarchy to which the following bits correspond. A sequence of repairs are encoded as string of bits. The bit which follows a complete repair encoding indicates whether a repair to the currently identified cache is indicated or whether a new cache is targeted by the following repair. Therefore, certain repairs may be encoded without respecifying the entire hierarchy.
摘要翻译： 用于对维修计算系统内的设备进行编码的分层编码格式。 诸如高速缓冲存储器的设备被逻辑地分割成多个子部分。 子部分的各个部分可被识别为设备的不同层级。 第一子部分可以对应于特定高速缓存，第二子部分可以对应于高速缓存的特定方式，等等。 编码格式包括一系列位，其中第一部分对应于层级的第一级，并且位的第二部分对应于层级的第二级。 位的第一和第二部分中的每一个前面都有一个不同的值，用于识别跟随位对应的层级。 维修序列被编码为位串。 遵循完整修复编码的位指示是否指示对当前标识的高速缓存的修复，或者是否通过以下修复来定位新的高速缓存。 因此，可以编码某些修复，而不需要重新整理层次结构。
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3.发明授权Resolving dependencies among concurrently dispatched instructions in a superscalar microprocessor 失效在超标量微处理器中解析并发调度指令之间的依赖关系公开(公告)号：US06542986B1
公开(公告)日：2003-04-01
申请号：US09437086
申请日：1999-11-09
申请人： Scott A. White
发明人： Scott A. White
IPC分类号： G06F938
CPC分类号： G06F9/382 , G06F9/30152 , G06F9/3816 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： A superscalar processor may issue multiple instructions per clock cycle. Included in a superscalar processor may be a reorder buffer which stores information corresponding to concurrently dispatched instructions. Dependencies may exist among the instructions which are concurrently dispatched. To resolve this dependency, when a dependency is detected amongst a group of concurrently dispatched instructions, an indication of the dependency, along with an indication of the position of the dependency, is conveyed to the corresponding reservation station. When the reservation station receives the indication of the dependency, the operand tag associated with the dependency may be replaced with the correct tag. Advantageously, the circuitry needed to resolve the dependency may be moved out of the critical path of the processor; thus, improving the performance of the processor by allowing it to operate at an increased frequency.
摘要翻译： 超标量处理器可以在每个时钟周期发出多个指令。 包含在超标量处理器中可以是重排序缓冲器，其存储与并发分派指令相对应的信息。 在同时发送的指令之间可能存在依赖关系。 为了解决这种依赖性，当在一组并行调度的指令中检测到依赖性时，依赖关系的指示连同依赖关系的位置的指示被传送到相应的保留站。 当保留站接收到依赖关系的指示时，与依赖关联的操作数标签可以被替换为正确的标签。 有利的是，解决依赖性所需的电路可以被移出处理器的关键路径; 因此，通过允许其以增加的频率操作来提高处理器的性能。
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公开(公告)号：US5857089A
公开(公告)日：1999-01-05
申请号：US967950
申请日：1997-11-12
申请人： Michael D. Goddard , Scott A. White
发明人： Michael D. Goddard , Scott A. White
CPC分类号： G06F7/785 , G06F9/30032 , G06F9/3004 , G06F9/30112 , G06F9/30134 , G06F9/3806 , G06F9/3836 , G06F9/384 , G06F9/3842 , G06F9/3844 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3885
摘要： In a processor (110) that performs multiple instructions in a single cycle, predicts outcomes of branch conditions and speculatively executes instructions based on the branch predictions, a method and apparatus for operating a data stack utilize a remap array (674) to support a stack exchange capability. The remap array is used to correlate a stack pointer (672) to data elements (700) within the stack. A lookahead stack pointer (502) and remap array (504) are updated to preserve the processor's state of operation while speculative instructions are executed.
摘要翻译： 在单个周期中执行多个指令的处理器（110）中，预测分支条件的结果并基于分支预测推测地执行指令，用于操作数据堆栈的方法和装置利用重映射阵列（674）来支持堆栈 交换能力。 重映射数组用于将堆栈指针（672）与堆栈内的数据元素（700）相关联。 更新前瞻堆栈指针（502）和重新映射数组（504）以在执行推测性指令时保持处理器的操作状态。
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公开(公告)号：US5737629A
公开(公告)日：1998-04-07
申请号：US671439
申请日：1996-06-27
CPC分类号： G06F9/30043 , G06F9/30014 , G06F9/30036 , G06F9/30112 , G06F9/30192 , G06F9/3824 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： A pipelined or superscalar processor (10) that executes operations utilizing operand data of variable bit widths improves parallel performance by partitioning a fixed bit width operand (200) into several partial operand fields (215, 216 and 217), and checking for data dependencies, tagging and forwarding data in these fields independently of one another. An instruction decoder (18) concurrently dispatches multiple ROPs to various functional units (20, 21, 22 and 80). Conflicts which arise with respect to register resources are resolved through register renaming. However, implementation of register renaming is difficult when register structures are overlapping. The present invention supports independent dependency checking, tagging and forwarding of partial bit fields of a register operand which, in combination, allow renaming of registers. Therefore, the variable width register operand structure greatly assists the processor to resolve data dependencies. Operands are tagged by a reorder buffer (26) and supplied with data when it becomes available without regard for the type of data. This method of dependency resolution supports parallel performance of operations and provides a substantial improvement in overall speed of processing. Thus, the processor promotes parallel processing of operations that act upon overlapping data structures which otherwise resist parallel handling.
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公开(公告)号：US06442707B1
公开(公告)日：2002-08-27
申请号：US09430120
申请日：1999-10-29
IPC分类号： H02H305
CPC分类号： G06F9/3861 , G06F9/32
摘要： In a processor a reorder buffer maintains a load/store (LS) fault address register (LSFAR). When the processor's load/store unit reports most LS exceptions, the reorder buffer redirects the microcode unit of the processor to execute a fault handler indicated by an address stored in the LSFAR. The LSFAR may be mapped into the register space of the processor. It may be written by a microcode routine with the address of a specific fault handler at the beginning of a microcode routine or at any time during a microcode routine. As the reorder buffer retires instructions it checks for writes to the LSFAR. If one exists, the reorder buffer loads the result data of that write into the LSFAR. In a preferred embodiment the reorder buffer retires instructions in program order and the LSFAR is not updated speculatively. Also, in a preferred embodiment, when a microcode routine exits, the LSFAR is automatically returned to a default value which indicates a generic fault handling routine.
摘要翻译： 在处理器中，重排序缓冲器维护加载/存储（LS）故障地址寄存器（LSFAR）。 当处理器的加载/存储单元报告大多数LS异常时，重排序缓冲区重定向处理器的微代码单元，以执行由存储在LSFAR中的地址指示的故障处理程序。 LSFAR可以映射到处理器的寄存器空间。 微代码程序可以在微代码程序的开始处或在微代码程序中的任何时间由具有特定故障处理程序的地址的微代码程序写入。 当重新排序缓冲区退出指令时，它会检查对LSFAR的写入。 如果存在，则重新排序缓冲区将该写入的结果数据加载到LSFAR中。 在优选实施例中，重新排序缓冲器以程序顺序退出指令，LSFAR不被推测更新。 此外，在优选实施例中，当微代码例程退出时，LSFAR自动返回到指示通用故障处理例程的默认值。
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7.发明授权Superscalar microprocessor including flag operand renaming and forwarding apparatus 失效超标量微处理器包括标志操作数重命名和转发设备
公开(公告)号：US5805853A
公开(公告)日：1998-09-08
申请号：US799064
申请日：1997-02-10
CPC分类号： G06F9/30094 , G06F9/3836 , G06F9/384 , G06F9/3842 , G06F9/3855 , G06F9/3857 , G06F9/3863
摘要： A superscalar microprocessor is provided with a reorder buffer for storing the speculative state of the microprocessor and a register file for storing the real state of the microprocessor. A flags register stores the real state of flags that are updated by flag modifying instructions which are executed by the functional units of the microprocessor. To enhance the performance of the microprocessor with respect to conditional branching instructions, the reorder buffer includes a flag storage area for storing flags that are updated by flag modifying instructions. The flags are renamed to make possible the earlier execution of branch instructions which depend on flag modifying instructions. If a flag is not yet determined, then a flag tag is associated with the flag storage area in place of that flag until the actual flag value is determined. A flag operand bus and a flag tag bus are provided between the flag storage area and the branching functional unit so that the requested flag or flag tags are provided to instructions which are executed in the branching functional unit.
摘要翻译： 超标量微处理器设置有用于存储微处理器的推测状态的重排序缓冲器和用于存储微处理器的实际状态的寄存器文件。 标志寄存器存储由微处理器的功能单元执行的标志修改指令更新的标志的实际状态。 为了提高微处理器相对于条件转移指令的性能，重排序缓冲器包括一个标志存储区域，用于存储通过标志修改指令更新的标志。 这些标志被重命名，以便能够更早地执行依赖于标志修改指令的分支指令。 如果尚未确定标志，则标志标签与标志存储区域相关联，而不是该标志，直到确定了实际标志值。 在标志存储区域和分支功能单元之间提供标志操作数总线和标志标签总线，使得所请求的标志或标志标签被提供给在分支功能单元中执行的指令。
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8.发明授权Range finding circuit for selecting a consecutive sequence of reorder buffer entries using circular carry lookahead 失效测距电路，用于使用循环进位先行选择连续的重排序缓冲器序列序列
公开(公告)号：US5689693A
公开(公告)日：1997-11-18
申请号：US233568
申请日：1994-04-26
申请人： Scott A. White
发明人： Scott A. White
CPC分类号： G06F7/764 , B24B37/042 , G06F7/74 , G06F9/30018
摘要： A enable circuit (700), employing a "circular carry lookahead" technique to increase its speed performance, is provided for applying two pointers to a circular buffer--an enabling pointer (tail (218)) and a disabling pointer (head (216))--and for generating a multiple-bit enable, ENA (722) in accordance with the pointer values. The pointers designate enable bit boundaries for isolating enable bits of one logic level from enable bits of an opposite logic level. The enable circuit includes several lookahead cells (702, 704, 706 and 708) arranged in an hierarchical array, each of the cells including bits that continue the hierarchical significance. Each cell receives an hierarchical portion of the enabling pointer 218 and the disabling pointer head and a carry. From these pointers, the cell derives a generate, a propagate and the enable bits with a corresponding hierarchical significance. The propagates, generates and carries for all of the lookahead cells are interconnected using a circular propagate carry circuit (710) that provides for asserting a carry to a lookahead cell unless an intervening cell having a nonasserted propagate is interposed in the order of hierarchical significance between the cell and a cell in which enablement is generated.
摘要翻译： 提供了使用“循环进位前瞻”技术来增加其速度性能的使能电路（700），用于将两个指针应用于循环缓冲器 - 使能指针（尾部<3：0>（218））和禁用指针 （头<3：0>（216）） - 并且用于根据指针值产生多位使能ENA（722）。 指针指定使能位边界，用于将一个逻辑电平的使能位与相反逻辑电平的使能位隔离开。 使能电路包括以分层阵列布置的几个前视单元（702,704,706和708），每个单元包括继续层次重要性的位。 每个单元接收使能指针218和禁用指针头<3：0>和进位的分层部分。 从这些指针中，单元格导出生成，传播和具有相应层次重要性的使能位。 传播，产生和携带所有的前瞻性小区是使用环形传播携带电路（710）相互连接的，该环路传播携带电路（710）提供将前进小区的进位断言，除非具有非惰性传播的中间小区按照层次重要性的顺序插入 该单元和其中产生启用的单元。
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公开(公告)号：US5590352A
公开(公告)日：1996-12-31
申请号：US233567
申请日：1994-04-26
CPC分类号： G06F9/30043 , G06F9/30014 , G06F9/30036 , G06F9/30112 , G06F9/30192 , G06F9/3824 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： A pipelined or superscalar processor (10) that executes operations utilizing operand data of variable bit widths improves parallel performance by partitioning a fixed bit width operand (200) into several partial operand fields (215, 216 and 217), and checking for data dependencies, tagging and forwarding data in these fields independently of one another. An instruction decoder (18) concurrently dispatches multiple ROPs to various functional units (20, 21, 22 and 80). Conflicts which arise with respect to register resources are resolved through register renaming. However, implementation of register renaming is difficult when register structures are overlapping. The present invention supports independent dependency checking, tagging and forwarding of partial bit fields of a register operand which, in combination, allow renaming of registers. Therefore, the variable width register operand structure greatly assists the processor to resolve data dependencies. Operands are tagged by a reorder buffer (26) and supplied with data when it becomes available without regard for the type of data. This method of dependency resolution supports parallel performance of operations and provides a substantial improvement in overall speed of processing. Thus, the processor promotes parallel processing of operations that act upon overlapping data structures which otherwise resist parallel handling.
摘要翻译： 使用可变位宽的操作数数据执行操作的流水线或超标量处理器（10）通过将固定位宽操作数（200）划分成几个部分操作数字段（215,216和217）来提高并行性能，并且检查数据依赖性， 在这些字段中标记和转发数据，彼此独立。 指令解码器（18）同时将多个ROP调度到各种功能单元（20,21,22和80）。 通过注册重命名来解决与注册资源有关的冲突。 然而，当寄存器结构重叠时，实现寄存器重命名是困难的。 本发明支持对寄存器操作数的部分位字段的独立依赖性检查，标记和转发，其组合允许寄存器重命名。 因此，可变宽度寄存器操作数结构大大有助于处理器解决数据依赖性。 操作数由重排序缓冲器（26）标记，并在数据可用时提供数据，而不考虑数据类型。 这种依赖关系的方法支持并行的操作性能，并提供整体处理速度的实质性改进。 因此，处理器促进对重叠的数据结构起作用的操作的并行处理，否则其将抵抗并行处理。
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公开(公告)号：US4789284A
公开(公告)日：1988-12-06
申请号：US116954
申请日：1987-11-05
申请人： Scott A. White
发明人： Scott A. White
CPC分类号： F16B13/066 , E21D21/0053 , E21D21/008
摘要： The present invention relates to expansison anchors for solid wall installation and is specifically concerned with providing a self cutting expansion anchor which can be installed in one continuous motion by utilizing combined cutting blades and wall gripping members which cut their own undercut portion within a wall bore into which the gripping members are then permanently further expanded in positive locking engagement. Such dual-stage installation is achieved by utilizing an anchor mounting assembly having a pair or opposite-hand screw-threaded portions thereon which separately mount a blade expanding thrust member and a camming ramp on which the blades are initially expanded by axial movement of the thrust member toward the ramp and in the second stage causing the ramp to axially move toward the thrust member in further expanding relation to the blades.
摘要翻译： 本发明涉及用于固体壁安装的膨胀锚，并且特别涉及提供一种自切割膨胀锚，其可以通过利用组合的切割刀片和壁夹持构件来连续地安装，所述组合切割刀片和壁抓握构件在壁孔内切割自己的底切部分 其中夹持构件然后被永久地进一步扩大为正的锁定接合。 这样的双级安装是通过利用锚固安装组件来实现的，锚具安装组件具有一对或相反的螺纹螺纹部分，其分别安装有叶片膨胀推力构件和凸轮斜面，叶片最初通过推力轴向运动而膨胀 构件朝向斜坡并且在第二阶段中导致斜面朝向推力构件轴向移动，与叶片进一步扩展。
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