公开(公告)号：US6067655A

公开(公告)日：2000-05-23

申请号：US919868

申请日：1997-08-28

申请人： Janos Kovacs ,  Ronald Kroesen ,  Jason Byrne

发明人： Janos Kovacs ,  Ronald Kroesen ,  Jason Byrne

IPC分类号： H04R3/02 ,  H03M13/00

CPC分类号： H04R3/02

摘要： A burst error limiting symbol detector system includes a symbol detector circuit responsive to a truncated sample signal for detecting binary symbols encoded in a truncated sample signal with reference to at least one preselected reference level; a feedback equalizer circuit for providing a feedback equalizer signal for cancelling undesired samples in an input signal; a summing circuit, responsive to the input signal and the feedback equalizer signal for providing the truncated sample signal to the symbol detector circuit; and a feedback suppressor circuit responsive to the truncated sample being within a predetermined range of the preselected reference level for suppressing the feedback equalizer signal to prevent marginal detected binary symbols from contributing to the cancellation of undesired samples in the input signal.

摘要翻译： 突发错误限制符号检测器系统包括符号检测器电路，其响应于截取的采样信号，用于参考至少一个预选参考电平来检测以截断的采样信号编码的二进制符号; 反馈均衡器电路，用于提供用于消除输入信号中的不需要的采样的反馈均衡器信号; 响应于输入信号和反馈均衡器信号的加法电路，用于将截断的采样信号提供给符号检测器电路; 以及反馈抑制器电路，其响应于所述截断的样本在所述预选参考电平的预定范围内，以抑制所述反馈均衡器信号，以防止边缘检测到的二进制符号有助于消除所述输入信号中的不需要的采样。

公开(公告)号：US5768320A

公开(公告)日：1998-06-16

申请号：US523648

申请日：1995-09-05

申请人： Janos Kovacs ,  Ronald Kroesen ,  Philip Quinlan

发明人： Janos Kovacs ,  Ronald Kroesen ,  Philip Quinlan

IPC分类号： G11B5/09 ,  G11B20/10

CPC分类号： G11B20/10175 ,  G11B20/10009 ,  G11B5/09

摘要： A read system for implementing PR4 and higher order PRML signals includes: a continuous time programmable filter, for receiving a read signal representative of a binary signal from a storage medium and for shaping the read signal into a PR4 shaped read signal; an analog finite impulse response (AFIR) filter, responsive to the continuous time programmable filter, for sampling and forming the PR4 shaped read signal into a PR4 shaped multilevel read signal; an analog to digital converter, responsive to the AFIR filter, for converting the PR4 shaped multilevel read signal from analog to digital; a data sequence filter, responsive to the analog to digital converter, for transforming the PR4 shaped multilevel digital read signal to a predetermined order PRML signal; and a Viterbi detector, responsive to the data sequence filter, for detecting the binary signal from the predetermined order PRML signal.

摘要翻译： 用于实现PR4和更高阶PRML信号的读取系统包括：连续时间可编程滤波器，用于从存储介质接收表示二进制信号的读取信号，并将读取信号整形为PR4形读取信号; 响应于连续时间可编程滤波器的模拟有限脉冲响应（AFIR）滤波器，用于将PR4形读取信号采样并形成为PR4形多电平读信号; 响应于AFIR滤波器的模数转换器，用于将PR4形多级读取信号从模拟转换成数字; 响应于所述模数转换器的数据序列滤波器，用于将所述PR4形多级数字读信号转换成预定顺序PRML信号; 以及响应于数据序列滤波器的维特比检测器，用于检测来自预定顺序PRML信号的二进制信号。

公开(公告)号：US5646968A

公开(公告)日：1997-07-08

申请号：US560013

申请日：1995-11-17

申请人： Janos Kovacs ,  Ronald Kroesen ,  Kevin McCall

发明人： Janos Kovacs ,  Ronald Kroesen ,  Kevin McCall

IPC分类号： H03K3/0231 ,  H03K3/03 ,  H03L7/081 ,  H03L7/087 ,  H03L7/099 ,  H03L7/14 ,  H03D3/24

CPC分类号： H03K3/0231 ,  H03K3/03 ,  H03K3/0322 ,  H03L7/081 ,  H03L7/087 ,  H03L7/0996 ,  H03L7/14

摘要： A dynamic phase selector phase locked loop circuit includes: an A/D converter for receiving an input to be sampled; a phase detection circuit for determining the phase error between the input signal and a clock signal; a clock circuit, responsive to the phase detection circuit, for providing the clock signal to the A/D converter for timing the sampling of the input signal; the clock circuit including a delay circuit having a number of delay taps; and a phase selector circuit, responsive to the phase detection circuit, for initially gating the clock signals to the A/D converter from the clock circuit, and enabling one of the delay taps to dynamically adjust the phase of the clock signal and reduce the initial phase error.

摘要翻译： 动态相位选择器锁相环电路包括：A / D转换器，用于接收要采样的输入; 相位检测电路，用于确定输入信号和时钟信号之间的相位误差; 时钟电路，响应相位检测电路，用于将时钟信号提供给A / D转换器，用于对输入信号的采样进行定时; 所述时钟电路包括具有多个延迟抽头的延迟电路; 以及相位选择器电路，响应于相位检测电路，用于从时钟电路初始地将时钟信号选通到A / D转换器，并使得其中一个延迟抽头能够动态地调整时钟信号的相位并减少初始 相位误差。

公开(公告)号：US5495512A

公开(公告)日：1996-02-27

申请号：US314894

申请日：1994-09-29

申请人： Janos Kovacs ,  Ronald Kroesen

发明人： Janos Kovacs ,  Ronald Kroesen

IPC分类号： H03L7/08 ,  H03L7/087 ,  H03L7/093 ,  H03L7/099 ,  H03L7/107 ,  H03D3/24

CPC分类号： H03L7/107 ,  H03L7/093 ,  H03L7/099 ,  H03L2207/04

摘要： A phase locked loop system or other second order feedback system whose natural frequency scales with its output and whose damping factor remains constant includes a filter circuit having a scaling channel for scaling the error, an integrating channel for integrating the error, and a summing circuit for combining the scaled error and integrated error; an integrator circuit responsive to the summing circuit to produce an output signal, the gain of the integrator circuit being proportional to its output signal; and a control circuit for controlling the gain of the integrating channel proportional to the output signal and maintaining constant the ratio of and scaling the product of the unity gained frequency and the zero frequency of the feedback system to keep constant the damping factor and to scale the natural frequency of the feedback system with the output signal, respectively.

摘要翻译： 锁相环系统或其其它二阶反馈系统，其固有频率与其输出和其阻尼因子保持不变包括具有缩放误差缩放通道的滤波器电路，用于积分误差的积分通道和用于积分误差的积分通道 组合缩放误差和积分误差; 积分器电路，响应于求和电路产生输出信号，积分器电路的增益与其输出信号成比例; 以及控制电路，用于控制与输出信号成比例的积分通道的增益，并保持恒定的单位增益频率和反馈系统的零频率的乘积的比例并缩放，以保持阻尼因子的恒定并缩放 反馈系统的固有频率分别与输出信号。

公开(公告)号：US5414390A

公开(公告)日：1995-05-09

申请号：US304248

申请日：1994-09-12

申请人： Janos Kovacs ,  Ronald Kroesen

发明人： Janos Kovacs ,  Ronald Kroesen

IPC分类号： H03L7/08 ,  H03L7/087 ,  H03L7/093 ,  H03L7/099 ,  H03L7/107 ,  H03L7/07 ,  G11B20/10 ,  H03L7/10 ,  H03L7/18

CPC分类号： H03L7/107 ,  H03L7/093 ,  H03L7/099 ,  H03L2207/04

摘要： A center frequency controlled phase locked loop system includes a primary phase locked loop having a first voltage controlled oscillator including a first voltage to current converter whose output current drives a first current controlled oscillator to produce the primary clock signal to be locked onto an input signal; a second phase locked loop having a second voltage controlled oscillator including a second voltage to current converter whose output current drives a second current controlled oscillator to produce the synthesized clock signal whose frequency is approximately that of the input signal or integral multiple thereof; and a current copier circuit for copying the output current from the second voltage to current converter and delivering it to the first current controlled oscillator to maintain the center frequency of the first voltage controlled oscillator at approximately the output frequency of the synthesized clock signal.

摘要翻译： 中心频率控制锁相环系统包括主锁相环，其具有第一压控振荡器，该第一压控振荡器包括第一电压 - 电流转换器，其输出电流驱动第一电流控制振荡器以产生待锁定到输入信号上的主时钟信号; 第二锁相环具有包括第二电压/电流转换器的第二压控振荡器，所述第二压控振荡器的输出电流驱动第二电流控制振荡器以产生频率大约为输入信号或其整数倍的合成时钟信号; 以及当前的复印机电路，用于将输出电流从第二电压复制到电流转换器，并将其传送到第一电流控制振荡器，以将第一压控振荡器的中心频率保持在合成时钟信号的输出频率的近似值。

公开(公告)号：US07881309B2

公开(公告)日：2011-02-01

申请号：US10416036

申请日：2001-11-06

申请人： Jouni Pirhonen ,  Vesa Taivalantti ,  Krisztian Litkey ,  Mika Lindroos ,  Janos Kovacs ,  Esa Sarkama

发明人： Jouni Pirhonen ,  Vesa Taivalantti ,  Krisztian Litkey ,  Mika Lindroos ,  Janos Kovacs ,  Esa Sarkama

IPC分类号： H04L12/28

CPC分类号： H04W28/20 ,  H04L29/06027 ,  H04L65/103 ,  H04L65/104 ,  H04L65/1043 ,  H04L65/608 ,  H04L65/80 ,  H04W4/24 ,  H04W88/16

摘要： When a service is provided in a service stream between end devices controlling the service stream by using first protocol, there is also a need to control the service stream in the network via which the service stream is or is to be transmitted. The service stream is controlled in the network by utilizing first protocol messages which are separated (204) from other traffic transmitted in the network.

摘要翻译： 当通过使用第一协议在服务流中控制服务流的服务流中提供服务时，还需要控制网络中的服务流，通过该服务流来传送服务流。 通过利用与在网络中传输的其他流量分离（204）的第一协议消息，在网络中控制服务流。

公开(公告)号：US4576637A

公开(公告)日：1986-03-18

申请号：US651849

申请日：1984-09-18

申请人： Istvan Tamas ,  Szilard Riederauer ,  Janos Kovacs

发明人： Istvan Tamas ,  Szilard Riederauer ,  Janos Kovacs

IPC分类号： C22C33/04 ,  C21C5/52 ,  C22B1/24 ,  C22C33/00 ,  C22B4/00

CPC分类号： C22C33/003 ,  C21C5/5264 ,  C22B1/2406 ,  Y02P10/216

摘要： A process for the continuous preparation of silicon-base complex ferrous alloys from cheap raw materials by preparing a charge with a high electric resistance and reducing the same in an electric arc furnace. A charge is assembled which contains the total amount of carbon in a 0.82 to 0.99-fold quantity of that required to reduce all oxides of the charge to elements and achieving this carbon content by preparing pellets which, in addition to the binding material, contain(a) as oxide to be reduced in an amount of at least 50% by weight such oxides of only base-forming or only amphoteric or only acid-forming elements which form with each other compounds or eutectics melting above 1600.degree. C., and(b) a carbonaceous reducing agent and/or carbides in such an amount that the quantity of carbon is either 1.05 to 1.35 times higher than required to transform the oxides of the pellet to the carbides or 0.66 to 0.02-fold of the quantity required to reduce the oxides of the pellet to metallic elements, and assembling the charge(.alpha.) from pellets containing an excess of carbon and/or from lumpy carbides and(.beta.) from carbon-deficient pellets or from a lumpy oxide of a base-forming or amphoteric or acid-forming element and(.gamma.) from lumpy carbon carriers, and optionally(.delta.) from an iron additive, in the absence of boron trioxide.

摘要翻译： 一种通过在电弧炉中制备具有高电阻并在电弧炉中还原的方法从廉价原料连续制备硅基复合铁合金的方法。 组装电荷，其含有将元素中的所有电荷的所有氧化物还原并达到该碳含量所需的0.82至0.99倍的总量，通过制备除了粘结材料外还含有 a）氧化物以至少50重量％的量还原这样的氧化物，其仅形成成形或仅两性或仅有酸形成元素，彼此形成化合物或熔点高于1600℃的共晶体，和（ b）碳质还原剂和/或碳化物的量使得碳的量比将颗粒的氧化物转化为碳化物所需的量高1.05至1.35倍，或减少所需的量的0.66至0.02倍 颗粒的氧化物与金属元素组合，并且从含有过量碳和/或块状碳化物的颗粒和（β）从含碳缺陷的颗粒或由形成碱或两性的块状氧化物组装电荷（α） 或来自块状碳载体的（γ）和任选的来自铁添加剂的（δ），在不存在三氧化硼的情况下。

公开(公告)号：US08093537B2

公开(公告)日：2012-01-10

申请号：US12429473

申请日：2009-04-24

申请人： Horst Linn ,  Andras Vass ,  Ivanne Pallai ,  Gyula Fazekas ,  Janos Kovacs ,  Istvan Edes

发明人： Horst Linn ,  Andras Vass ,  Ivanne Pallai ,  Gyula Fazekas ,  Janos Kovacs ,  Istvan Edes

IPC分类号： H05B6/78 ,  A23L3/00

CPC分类号： H05B6/782 ,  A23L7/196 ,  A23L7/1975 ,  B65D2581/3422 ,  Y02A40/924 ,  Y02P60/833

摘要： A process for the production of short cooking time rice is characterized by that hulled rice of at least 10% moisture content, if required in packaging suitable for ready cooking, is heat treated for 1 to 30 minutes continuously or interrupted by equal or alternating capacity microwave radiation, to reach maximum 130° C. An apparatus for the production of short cooking time rice has a microwave furnace with a tunnel made from a suitable material, wherein the rice packed into packages is movable within the tunnel by a conveyor. Regarding the easy and short process, a remarkable energy saving is possible.

摘要翻译： 用于生产短烹饪时间米的方法的特征在于，如果在适合于准备烹饪的包装中需要，至少含有10％水分含量的水稻被连续热处理1至30分钟或通过相等或交替容量的微波中断 辐射，达到最高130℃。一种用于生产短烹饪时间米的设备具有由合适材料制成的隧道的微波炉，其中包装的米饭通过输送机在隧道内可移动。 关于简单和简短的过程，可以显着节能。

公开(公告)号：US20090206072A1

公开(公告)日：2009-08-20

申请号：US12429473

申请日：2009-04-24

申请人： Horst Linn ,  Andras Vass ,  Ivanne Pallai ,  Gyula Fazekas ,  Janos Kovacs ,  Istvan Edes

发明人： Horst Linn ,  Andras Vass ,  Ivanne Pallai ,  Gyula Fazekas ,  Janos Kovacs ,  Istvan Edes

IPC分类号： H05B6/78

CPC分类号： H05B6/782 ,  A23L7/196 ,  A23L7/1975 ,  B65D2581/3422 ,  Y02A40/924 ,  Y02P60/833

摘要： A process for the production of short cooking time rice is characterized by that hulled rice of at least 10% moisture content, if required in packaging suitable for ready cooking, is heat treated for 1 to 30 minutes continuously or interrupted by equal or alternating capacity microwave radiation, to reach maximum 130° C. An apparatus for the production of short cooking time rice comprises a microwave furnace with a tunnel made from a suitable material, wherein the rice packed into packages is movable within the tunnel by a conveyor. Regarding the easy and short process, a remarkable energy safing is possible.

摘要翻译： 用于生产短烹饪时间米的方法的特征在于，如果在适合于准备烹饪的包装中需要，至少含有10％水分含量的水稻被连续热处理1至30分钟或通过相等或交替容量的微波中断 辐射，达到最高130℃。一种用于生产短烹饪时间饭的设备包括具有由合适材料制成的隧道的微波炉，其中包装的米饭通过输送机在隧道内可移动。 关于简单和简短的过程，可以进行显着的能量保护。

公开(公告)号：US5793239A

公开(公告)日：1998-08-11

申请号：US920692

申请日：1997-08-29

申请人： Janos Kovacs ,  Kevin McCall

发明人： Janos Kovacs ,  Kevin McCall

IPC分类号： H03H11/26

CPC分类号： H03H11/265 ,  Y10T307/858

摘要： A composite load circuit for use within another circuit includes at least one amplifying transistor. The composite load circuit includes first and second transistors connected in parallel. Each load transistor has a gate that receives a common control voltage. Each load transistor also has a different turn-on threshold voltage. A resistor, connected in parallel with the load transistors, limits an effective impedance of the load transistors.

摘要翻译： 在另一电路内使用的复合负载电路包括至少一个放大晶体管。 复合负载电路包括并联连接的第一和第二晶体管。 每个负载晶体管具有接收公共控制电压的栅极。 每个负载晶体管也具有不同的导通阈值电压。 与负载晶体管并联连接的电阻限制了负载晶体管的有效阻抗。