公开(公告)号：US20070132111A1

公开(公告)日：2007-06-14

申请号：US11548704

申请日：2006-10-12

Applicant: Jeffrey Lien

Inventor： Jeffrey Lien

IPC: H01L23/28

CPC classification number: H01L21/56 ,  H01L23/4951 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/92147 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/05599

Abstract: A fine-sized chip package structure is disclosed to include a memory chip, a leadframe having a plurality of leads bilaterally arranged on the bottom surface of the memory chip, gold wires connected between respective bonding pads at the middle part of the bottom surface of the memory chip and respective stitches at the bottom surface of each rectangular block-like lead of the leadframe, and a molding compound locally molded on a part of the memory chip and a part of each leadframe with a difference of elevation between the bottom surface of the molding compound and the bottom surfaces of the leads of the leadframe for receiving a solder material used to bond the memory chip and the leadframe to a circuit board, preventing overflow of the solder material during bonding of the memory chip and the leadframe to the circuit board.

Abstract translation: 公开了一种精细尺寸的芯片封装结构，包括存储芯片，具有双面布置在存储芯片的底表面上的多个引线的引线框架，金线连接在位于存储芯片的底表面的中间部分的各个焊盘之间 存储器芯片和引线框架的每个矩形块状引线的底表面处的相应线迹，以及局部模制在存储芯片的一部分上的模制化合物和每个引线框架的一部分，其中， 用于接收用于将存储器芯片和引线框架结合到电路板的焊料材料的引线框架的引线的底表面，防止在将存储芯片和引线框架接合到电路板期间焊料材料的溢出 。

公开(公告)号：US20050116325A1

公开(公告)日：2005-06-02

申请号：US10959375

申请日：2004-10-07

Applicant: Jeffrey Lien

Inventor： Jeffrey Lien

IPC: H01L23/32 ,  H01L23/498 ,  H01R31/06 ,  H01L23/02

CPC classification number: H01L23/49833 ,  H01L23/49827 ,  H01L23/4985 ,  H01L23/49861 ,  H01L24/48 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  H01R31/06 ,  H01L2924/00015 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The present invention is related to a switching media for chip carrier device, the switching media has a flexible board, the flexible board has circuits and a plurality of connecting points by way of etching thereon, the connecting points are able to connect to any type of chip of integrated circuit electrically, another plurality of etched connecting points on a lower surface of the flexible board are capable of connecting to the chip carrier device electrically, the circuits thereon individually connect to the connecting points on an upper surface of the flexible board and the connecting points on the lower surface. It is convenient for that the flexible board can electrically connect to the chip carrier device while the flexible board is installed on the chip carrier device. Hence, the upper surface is able to be mounted by any type of integrated circuit chip to reach the purposes of any chip connecting to the chip carrier device by means of the flexible board and any chip being changeable anytime.

Abstract translation: 本发明涉及用于芯片载体装置的开关介质，开关介质具有柔性板，柔性板具有电路和多个连接点，通过其上的蚀刻，连接点能够连接到任何类型 集成电路芯片电连接在柔性板的下表面上的另外多个蚀刻的连接点能够电连接到芯片载体装置，其上的电路单独地连接到柔性板的上表面上的连接点，并且 连接点在下表面。 当柔性板安装在芯片载体装置上时，柔性板可以电连接到芯片载体装置是方便的。 因此，上表面能够通过任何类型的集成电路芯片来安装，以通过柔性板和随时随地更换的任何芯片达到连接到芯片载体装置的任何芯片的目的。

公开(公告)号：US20050227414A1

公开(公告)日：2005-10-13

申请号：US10959202

申请日：2004-10-07

Applicant: Jeffrey Lien

Inventor： Jeffrey Lien

IPC: H01L23/12 ,  H01L21/44 ,  H01L21/56 ,  H01L23/31 ,  H01L23/495

CPC classification number: H01L24/97 ,  H01L21/56 ,  H01L23/3114 ,  H01L23/4951 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A packaging method for integrated circuits comprising processes such as wafer grinding, wafer mount, wafer saw, die attach, etc., multiple singulated chips are each attached and assembled to leadframe unit, the leadframe unit is used as electrical out-connecting component for each chip, and the wire-bonding part of the chip is dispensed continuously with encapsulant material to seal, curing method is further applied to solidify the encapsulant, then saw or punching method is used to dice apart each chip accompanied with leadframe unit (singulation process), a ready-to-use integrated circuit is thus obtained, such manufacturing processes let the goals of easy-to-manufacture, fast production and lowered-production cost be easily achieved for the packaging and singulating processes.

Abstract translation: 包括诸如晶片研磨，晶片安装，晶片锯，芯片附接等的多个单片芯片的集成电路的封装方法分别被附接并组装到引线框架单元，引线框架单元用作各自的电连接部件 芯片，芯片的引线接合部分用密封剂材料连续分配，进一步应用固化方法固化密封剂，然后使用锯切或冲孔方法将每个芯片分别与引线框架单元（分割工艺）分开， ，因此获得了即用型集成电路，这样的制造工艺使得容易制造，快速生产和降低生产成本的目标容易实现包装和分离工艺。

公开(公告)号：US20050224927A1

公开(公告)日：2005-10-13

申请号：US10959204

申请日：2004-10-07

Applicant: Jeffrey Lien

Inventor： Jeffrey Lien

IPC: H01L23/10 ,  H01L23/31 ,  H01L23/495 ,  H01L23/52

CPC classification number: H01L24/83 ,  H01L23/3114 ,  H01L23/4951 ,  H01L23/49513 ,  H01L24/48 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/83101 ,  H01L2224/838 ,  H01L2224/92147 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A chip fixed structure which is aiming at the better design of the adhesive body between the chip and the finger of the lead frame as well as its composite structure, which is to make said adhesive body with adhesion to form the stripe shapes with its width relatively smaller than the finger, through this to paste & settles a plurality of adhesive body on the upper lead facet of its dual-arrows or four-arrows fingers, also makes a chip pasting on the adhesive body which makes each arrow of lead frame carrying a chip and composite a fixed adhesive structure, so that it forms a structure with its width relatively smaller than the lead frame through said adhesive body as well as its composite formation, which allows the physical or chemical influences by the temperature change, thus maintaining the quality of chip as well as its usage lives.

Abstract translation: 一种芯片固定结构，其目的是在引线框架的芯片和指状物之间的粘合体的更好设计以及其复合结构，其是使所述粘合体具有粘附性以形成其宽度相对的条纹形状 小于手指，通过这种方式将多个粘合体粘贴在其双箭头或四箭头指的上引导面上，也使粘贴体上的芯片粘贴，使引线框架的每个箭头承载着 芯片和复合固定的粘合剂结构，使得其通过所述粘合体形成其宽度比引线框架小的结构以及其复合结构，其允许由温度变化的物理或化学影响，从而保持质量 的芯片以及其使用寿命。

公开(公告)号：US20070275574A1

公开(公告)日：2007-11-29

申请号：US11836126

申请日：2007-08-08

Applicant: Jeffrey Lien

Inventor： Jeffrey Lien

IPC: H01R12/02

CPC classification number: H05K7/1053

Abstract: The present invention provides a chip assembly structure with a cover, comprising: a socket having four sidewalls to form a room for placing a chip and comprising a plurality of contact ends corresponding to the contacts of the chip to be placed, wherein each contact ends penetrates said socket to form an exposing solder terminal; and a cover having at least a flexible part against on the chip when the chip is positioned in the room.

Abstract translation: 本发明提供一种具有盖的芯片组装结构，包括：具有四个侧壁的插座，用于形成用于放置芯片的房间，并且包括对应于要放置的芯片的触点的多个接触端，其中每个接触端穿透 所述插座形成露出焊接端子; 以及当芯片定位在房间中时，至少具有抵抗芯片上的柔性部分的盖子。

公开(公告)号：US20050179119A1

公开(公告)日：2005-08-18

申请号：US10959192

申请日：2004-10-07

Applicant: Jeffrey Lien

Inventor： Jeffrey Lien

IPC: H01L23/10 ,  H01L23/31 ,  H01L23/495

CPC classification number: H01L23/4951 ,  H01L23/3114 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4826 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2924/01014 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A miniaturized chip scale package is provided for the improvement of conventional chip package issues such as bulky packaged volume and bad heat dissipation. This invention provides a leadframe comprising multiple block leads for semiconductor die attachment. Conducting metallic wires are used to connect all the block leads of the leadframe to the chip, then the metallic conducting wire part is specifically encapsulated with insulating material to further form a miniaturized encapsulated body. The encapsulated body fully enclose the wire bonding part and at least an out-connecting electrical conducting part is preserved on the lower part of the lead such that the final packaged volume is reduced, heat dissipation efficiency is enhanced, and the chip transfer speed to the outside is enhanced due to a reduction in the transfer distance by the rectangular block leads structure design.

Abstract translation: 提供了一种小型化的芯片级封装，用于改进常规芯片封装问题，例如体积大的封装体积和不良散热。 本发明提供了一种引线框架，其包括用于半导体管芯附接的多个块引线 使用导电金属线将引线框架的所有块引线连接到芯片，然后金属导线部分用绝缘材料进行特别封装，以进一步形成小型封装体。 封装体完全封闭引线接合部分，并且至少一个外接导电部分保存在引线的下部，使得最终封装体积减小，散热效率提高，芯片传输速度提高到 外部由于通过矩形块引线结构设计的传输距离减小而得到增强。

公开(公告)号：US07138704B2

公开(公告)日：2006-11-21

申请号：US10959207

申请日：2004-10-07

Applicant: Jeffrey Lien ,  Yuan Sheng Cheng

Inventor： Jeffrey Lien ,  Yuan Sheng Cheng

IPC: H01L23/48

CPC classification number: H01L23/49551 ,  H01L23/3114 ,  H01L23/4951 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/32245 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/4826 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A concealable chip leadframe unit structure is disclosed which is made up of multiple lead units arranged in order, each lead in the lead unit is formed by pressing and comprising of a piece body with upper placement plane, the lower surface of the piece body is pressed to form at least an inner conducting plane which can be connected to the chip, and at least one protruding bump is formed adjacent to the inner conducting plane, the end surface of the protruding bump is used as an out-conducting plane to be connected to outside; in this structure, chip can be attached to the upper placement plane of the lead structure, and the inner conducting plane can be connected to the chip through metallic wire.

Abstract translation: 公开了一种可隐藏的芯片引线框单元结构，其由依次布置的多个引线单元构成，引线单元中的每个引线通过压制形成，并且包括具有上放置平面的片体，片体的下表面被按压 至少形成能够连接到芯片的内部导电平面，并且与内部导电平面相邻地形成至少一个突出凸块，突出凸起的端面用作与外部导电平面连接的导电平面 外; 在该结构中，芯片可以安装在引线结构的上部放置平面上，并且内部导电平面可以通过金属线连接到芯片。

公开(公告)号：US07074651B2

公开(公告)日：2006-07-11

申请号：US10959202

申请日：2004-10-07

Applicant: Jeffrey Lien

Inventor： Jeffrey Lien

IPC: H01L21/44

CPC classification number: H01L24/97 ,  H01L21/56 ,  H01L23/3114 ,  H01L23/4951 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A packaging method for integrated circuits comprising processes such as wafer grinding, wafer mount, wafer saw, die attach, etc., multiple singulated chips are each attached and assembled to leadframe unit, the leadframe unit is used as electrical out-connecting component for each chip, and the wire-bonding part of the chip is dispensed continuously with encapsulant material to seal, curing method is further applied to solidify the encapsulant, then saw or punching method is used to dice apart each chip accompanied with leadframe unit (singulation process), a ready-to-use integrated circuit is thus obtained, such manufacturing processes let the goals of easy-to-manufacture, fast production and lowered-production cost be easily achieved for the packaging and singulating processes.

Abstract translation: 包括诸如晶片研磨，晶片安装，晶片锯，芯片附接等的多个单片芯片的集成电路的封装方法分别被附接并组装到引线框单元，引线框单元用作每个 芯片，芯片的引线接合部分用密封剂材料连续分配，进一步应用固化方法固化密封剂，然后使用锯切或冲孔方法将每个芯片分别与引线框架单元（分割工艺）分开， ，因此获得了即用的集成电路，这样的制造工艺使得容易制造，快速生产和降低生产成本的目标容易实现包装和分离工艺。

公开(公告)号：US20060051899A1

公开(公告)日：2006-03-09

申请号：US11059418

申请日：2005-02-17

Applicant: Jeffrey Lien

Inventor： Jeffrey Lien

IPC: H01L21/50

CPC classification number: H01L23/3114 ,  H01L23/4951 ,  H01L23/49582 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method of forming precision leads on a chip-supporting leadframe includes the step of having each of the leads plated at a lower side with a metal substance to directly form one or more conducting sections and outer conducting planes, such that the non-plated area of the lower side of each lead defines an inner conducting plane for electrically conductively contacting with a chip supported on a top of the leadframe. The conducting sections and the outer conducting planes directly plated on the leads have precise and stable sizes and allow the leadframe to have a reduced volume. The metal substance for plating maybe gold, silver, copper, etc., depending on actual need, so as to increase the conductivity and reduce the resistance of the leads.

Abstract translation: 在芯片支撑引线框架上形成精密引线的方法包括以下步骤：将具有金属物质的下侧的每个引线直接形成一个或多个导电部分和外部导电平面，使得非镀覆区域 每个引线的下侧限定了用于与支撑在引线框的顶部上的芯片导电接触的内部导电平面。 直接电镀在引线上的导电部分和外部导电平面具有精确和稳定的尺寸，并允许引线框架具有减小的体积。 根据实际需要，用于电镀的金属物质可以是金，银，铜等，以增加导电性并降低引线的电阻。

公开(公告)号：US20050156289A1

公开(公告)日：2005-07-21

申请号：US10959206

申请日：2004-10-07

Applicant: Jeffrey Lien

Inventor： Jeffrey Lien

IPC: H01L25/10 ,  H01L23/495 ,  H01L23/498 ,  H01L23/50 ,  H01L23/538 ,  H01L25/18

CPC classification number: H01L23/5386 ,  H01L23/49572 ,  H01L24/48 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor chip leadframe module is disclosed, it is to provide selectively installed and directly connected common electrical leads among multiple leadframe units, and to provide independent electrical leads which can be connected respectively to circuit board (such as printed circuit board), the leadframe module thus formed provide space for the assembly of multiple chips, and the common signals on the chips can be connected to common electrical leads and then transferred to the circuit board, in contrary, the independent signals are transferred by the circuit board through independent electrical leads, the circuit board used layers and the amount of circuit layouts can thus be reduced, circuit board of lighter weight and smaller form factor can thus be achieved, furthermore, the saving in the usage of the circuit board space further provides more room for the plan and implementation of other functional structures or devices, etc.

Abstract translation: 公开了一种半导体芯片引线框模块，其是在多个引线框单元之间提供选择性地安装和直接连接的公共电引线，并且提供独立的电引线，其可分别连接到电路板（例如印刷电路板），引线框模块 这样形成为多个芯片的组装提供空间，并且芯片上的公共信号可以连接到公共电引线，然后传送到电路板，相反，独立信号由电路板通过独立的电引线传输， 电路板使用层，因此可以减少电路布局的数量，从而可以实现更轻的电路板和更小的外形尺寸，此外，节省电路板空间的使用进一步为计划和 实施其他功能结构或设备等