公开(公告)号：US20070281413A1

公开(公告)日：2007-12-06

申请号：US11840795

申请日：2007-08-17

申请人： Jinghong Li ,  Yaocheng Liu ,  Zhijiong Luo ,  Anita Madan ,  Nivo Rovedo

发明人： Jinghong Li ,  Yaocheng Liu ,  Zhijiong Luo ,  Anita Madan ,  Nivo Rovedo

IPC分类号： H01L21/8238

CPC分类号： H01L21/823814 ,  H01L21/26506 ,  H01L21/324 ,  H01L21/823807 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848 ,  Y10S257/90

摘要： The present invention relates to a semiconductor device comprising at least one n-channel field effect transistor (n-FET). Specifically, the n-FET comprises first and second patterned stressor layers that both contain a carbon-substituted and tensilely stressed single crystal semiconductor. The first patterned stressor layer has a first carbon concentration and is located in source and drain (S/D) extension regions of the n-FET at a first depth. The second patterned stressor layer has a second, higher carbon concentration and is located in S/D regions of the n-FET at a second, deeper depth. Such an n-FET with the first and second patterned stressor layers of different carbon concentration and different depths provide improved stress profile for enhancing electron mobility in the channel region of the n-FET.

摘要翻译： 本发明涉及包括至少一个n沟道场效应晶体管（n-FET）的半导体器件。 具体地说，n-FET包括第一和第二图案应力层，它们都包含碳取代和拉伸应力单晶半导体。 第一图案应力层具有第一碳浓度并且位于第一深度处的n-FET的源极和漏极（S / D）延伸区域中。 第二图案应力层具有第二较高的碳浓度，并且位于第二较深深度处的n-FET的S / D区中。 这种具有不同碳浓度和不同深度的第一和第二图案应力层的n-FET提供了改善的应力分布，用于增强n-FET的沟道区域中的电子迁移率。

公开(公告)号：US07279758B1

公开(公告)日：2007-10-09

申请号：US11420047

申请日：2006-05-24

申请人： Jinghong H. Li ,  Yaocheng Liu ,  Zhijiong Luo ,  Anita Madan ,  Nivo Rovedo

发明人： Jinghong H. Li ,  Yaocheng Liu ,  Zhijiong Luo ,  Anita Madan ,  Nivo Rovedo

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L21/823814 ,  H01L21/26506 ,  H01L21/324 ,  H01L21/823807 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848 ,  Y10S257/90

摘要： The present invention relates to a semiconductor device including at least one n-channel field effect transistor (n-FET). Specifically, the n-FET includes first and second patterned stressor layers that both contain a carbon-substituted and tensilely stressed single crystal semiconductor. The first patterned stressor layer has a first carbon concentration and is located in source and drain (S/D) extension regions of the n-FET at a first depth. The second patterned stressor layer has a second, higher carbon concentration and is located in S/D regions of the n-FET at a second, deeper depth. Such an n-FET with the first and second patterned stressor layers of different carbon concentration and different depths provide improved stress profile for enhancing electron mobility in the channel region of the n-FET.

摘要翻译： 本发明涉及包括至少一个n沟道场效应晶体管（n-FET）的半导体器件。 具体地说，n-FET包括均包含碳取代和拉伸应力单晶半导体的第一和第二图案应力层。 第一图案应力层具有第一碳浓度并且位于第一深度处的n-FET的源极和漏极（S / D）延伸区域中。 第二图案应力层具有第二较高的碳浓度，并且位于第二较深深度处的n-FET的S / D区中。 这种具有不同碳浓度和不同深度的第一和第二图案应力层的n-FET提供了改善的应力分布，用于增强n-FET的沟道区域中的电子迁移率。

公开(公告)号：US07473608B2

公开(公告)日：2009-01-06

申请号：US11840795

申请日：2007-08-17

申请人： Jinghong H. Li ,  Yaocheng Liu ,  Zhijiong Luo ,  Anita Madan ,  Nivo Rovedo

发明人： Jinghong H. Li ,  Yaocheng Liu ,  Zhijiong Luo ,  Anita Madan ,  Nivo Rovedo

IPC分类号： H01L21/22

CPC分类号： H01L21/823814 ,  H01L21/26506 ,  H01L21/324 ,  H01L21/823807 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848 ,  Y10S257/90

摘要： The present invention relates to a semiconductor device comprising at least one n-channel field effect transistor (n-FET). Specifically, the n-FET comprises first and second patterned stressor layers that both contain a carbon-substituted and tensilely stressed single crystal semiconductor. The first patterned stressor layer has a first carbon concentration and is located in source and drain (S/D) extension regions of the n-FET at a first depth. The second patterned stressor layer has a second, higher carbon concentration and is located in S/D regions of the n-FET at a second, deeper depth. Such an n-FET with the first and second patterned stressor layers of different carbon concentration and different depths provide improved stress profile for enhancing electron mobility in the channel region of the n-FET.

摘要翻译： 本发明涉及包括至少一个n沟道场效应晶体管（n-FET）的半导体器件。 具体地说，n-FET包括第一和第二图案应力层，它们都包含碳取代和拉伸应力单晶半导体。 第一图案应力层具有第一碳浓度并且位于第一深度处的n-FET的源极和漏极（S / D）延伸区域中。 第二图案应力层具有第二较高的碳浓度，并且位于第二较深深度处的n-FET的S / D区中。 这种具有不同碳浓度和不同深度的第一和第二图案应力层的n-FET提供了改善的应力分布，用于增强n-FET的沟道区域中的电子迁移率。

公开(公告)号：US20100059764A1

公开(公告)日：2010-03-11

申请号：US12618152

申请日：2009-11-13

申请人： Zhijiong Luo ,  Ricky S. Amos ,  Nivo Rovedo ,  Henry K. Utomo

发明人： Zhijiong Luo ,  Ricky S. Amos ,  Nivo Rovedo ,  Henry K. Utomo

IPC分类号： H01L29/78 ,  H01L29/24

CPC分类号： H01L29/7848 ,  H01L21/26513 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66636

摘要： A multilayer embedded stressor having a graded dopant profile for use in a semiconductor structure for inducing strain on a device channel region is provided. The inventive multilayer stressor is formed within areas of a semiconductor structure in which source/drain regions are typically located. The inventive multilayer stressor includes a first conformal epi semiconductor layer that is undoped or lightly doped and a second epi semiconductor layer that is highly dopant relative to the first epi semiconductor layer. The first and second epi semiconductor layers each have the same lattice constant, which is different from that of the substrate they are embedded in. The structure including the inventive multilayer embedded stressor achieves a good balance between stress proximity and short channel effects, and even eliminates or substantially reduces any possible defects that are typically generated during formation of the deep source/drain regions.

摘要翻译： 提供了具有用于在器件沟道区域上诱发应变的半导体结构中的渐变掺杂物分布的多层嵌入式应力器。 本发明的多层应力器形成在源极/漏极区域通常位于其中的半导体结构的区域内。 本发明的多层应力器包括未掺杂或轻掺杂的第一共形外延半导体层和相对于第一外延半导体层高度掺杂的第二外延半导体层。 第一和第二外延半导体层各自具有相同的晶格常数，其不同于嵌入其中的衬底。包括本发明的多层嵌入式应力器的结构在应力接近和短沟道效应之间实现良好的平衡，甚至消除 或基本上减少在深源/漏区形成期间通常产生的任何可能的缺陷。

公开(公告)号：US07618866B2

公开(公告)日：2009-11-17

申请号：US11423227

申请日：2006-06-09

申请人： Zhijiong Luo ,  Ricky S. Amos ,  Nivo Rovedo ,  Henry K. Utomo

发明人： Zhijiong Luo ,  Ricky S. Amos ,  Nivo Rovedo ,  Henry K. Utomo

IPC分类号： H01L21/336

CPC分类号： H01L29/7848 ,  H01L21/26513 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66636

摘要： A multilayer embedded stressor having a graded dopant profile for use in a semiconductor structure for inducing strain on a device channel region is provided. The inventive multilayer stressor is formed within areas of a semiconductor structure in which source/drain regions are typically located. The inventive multilayer stressor includes a first conformal epi semiconductor layer that is undoped or lightly doped and a second epi semiconductor layer that is highly dopant relative to the first epi semiconductor layer. The first and second epi semiconductor layers each have the same lattice constant, which is different from that of the substrate they are embedded in. The structure including the inventive multilayer embedded stressor achieves a good balance between stress proximity and short channel effects, and even eliminates or substantially reduces any possible defects that are typically generated during formation of the deep source/drain regions.

摘要翻译： 提供了具有用于在器件沟道区域上诱发应变的半导体结构中的渐变掺杂物分布的多层嵌入式应力器。 本发明的多层应力器形成在源极/漏极区域通常位于其中的半导体结构的区域内。 本发明的多层应力器包括未掺杂或轻掺杂的第一共形外延半导体层和相对于第一外延半导体层高度掺杂的第二外延半导体层。 第一和第二外延半导体层各自具有相同的晶格常数，其不同于嵌入其中的衬底。包括本发明的多层嵌入式应力器的结构在应力接近和短沟道效应之间实现良好的平衡，甚至消除 或基本上减少在深源/漏区形成期间通常产生的任何可能的缺陷。

公开(公告)号：US07442619B2

公开(公告)日：2008-10-28

申请号：US11383965

申请日：2006-05-18

申请人： Zhijiong Luo ,  Huilong Zhu ,  Yung Fu Chong ,  Hung Y. Ng ,  Kern Rim ,  Nivo Rovedo

发明人： Zhijiong Luo ,  Huilong Zhu ,  Yung Fu Chong ,  Hung Y. Ng ,  Kern Rim ,  Nivo Rovedo

IPC分类号： H01L21/283 ,  H01L23/482

CPC分类号： H01L21/823814 ,  H01L21/823871 ,  H01L21/823878 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing a semiconductor device having a substantially L-shaped silicide element forming a contact is disclosed. The substantially L-shaped silicide element, inter alia, reduces contact resistance and may allow increased density of CMOS circuits. In one embodiment, the substantially L-shaped silicide element includes a base member and an extended member, wherein the base member extends at least partially into a shallow trench isolation (STI) region such that a substantially horizontal surface of the base member directly contacts a substantially horizontal surface of the STI region; and a contact contacting the substantially L-shaped silicide element. The contact may include a notch region for mating with the base member and a portion of the extended member, which increases the silicide-to-contact area and reduces contact resistance. Substantially L-shaped silicide element may be formed about a source/drain region, which increases the silicon-to-silicide area, and reduces crowding and contact resistance.

摘要翻译： 公开了一种制造具有形成接触的大致L形硅化物元件的半导体器件的方法。 基本上L形的硅化物元件尤其降低了接触电阻并且可以允许增加的CMOS电路的密度。 在一个实施例中，基本上L形的硅化物元件包括基底构件和延伸构件，其中基底构件至少部分地延伸到浅沟槽隔离（STI）区域中，使得基底构件的基本水平的表面直接接触 STI区域的基本水平的表面; 以及接触基本上L形的硅化物元件的接触。 触点可以包括用于与基底构件和延伸构件的一部分配合的切口区域，这增加了硅化物与接触面积并降低了接触电阻。 可以围绕源极/漏极区域形成基本上L形的硅化物元素，这增加了硅 - 硅化物面积，并且减少了拥挤和接触电阻。

公开(公告)号：US20080283934A1

公开(公告)日：2008-11-20

申请号：US12182212

申请日：2008-07-30

申请人： Zhijiong Luo ,  Huilong Zhu ,  Yung Fu Chong ,  Hung Y. Ng ,  Kern Rim ,  Nivo Rovedo

发明人： Zhijiong Luo ,  Huilong Zhu ,  Yung Fu Chong ,  Hung Y. Ng ,  Kern Rim ,  Nivo Rovedo

IPC分类号： H01L29/78 ,  H01L21/44

CPC分类号： H01L21/823814 ,  H01L21/823871 ,  H01L21/823878 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure, semiconductor device and method having a substantially L-shaped silicide element for a contact are disclosed. The substantially L-shaped silicide element, inter alia, reduces contact resistance and may allow increased density of CMOS circuits. In one embodiment, the structure includes a substantially L-shaped silicide element including a base member and an extended member, wherein the base member extends at least partially into a shallow trench isolation (STI) region such that a substantially horizontal surface of the base member directly contacts a substantially horizontal surface of the STI region; and a contact contacting the substantially L-shaped silicide element. The contact may include a notch region for mating with the base member and a portion of the extended member, which increases the silicide-to-contact area and reduces contact resistance. Substantially L-shaped silicide element may be formed about a source/drain region, which increases the silicon-to-silicide area, and reduces crowding and contact resistance.

摘要翻译： 公开了具有用于接触的大致L形硅化物元件的结构，半导体器件和方法。 基本上L形的硅化物元件尤其降低了接触电阻并且可以允许增加的CMOS电路的密度。 在一个实施例中，该结构包括基本上为L形的硅化物元件，其包括基底构件和延伸构件，其中基底构件至少部分地延伸到浅沟槽隔离（STI）区域中，使得基底构件的基本水平的表面 直接接触STI区域的基本水平的表面; 以及接触基本上L形的硅化物元件的接触。 触点可以包括用于与基底构件和延伸构件的一部分配合的切口区域，这增加了硅化物与接触面积并降低了接触电阻。 可以围绕源极/漏极区域形成基本上L形的硅化物元素，这增加了硅 - 硅化物面积，并且减少了拥挤和接触电阻。

公开(公告)号：US20070293016A1

公开(公告)日：2007-12-20

申请号：US11424076

申请日：2006-06-14

申请人： Zhijiong Luo ,  Hung Y. Ng ,  Nivo Rovedo ,  Phung T. Nguyen ,  William C. Wille ,  Richard Lindsay ,  Zhao Lun ,  Yung Fu Chong ,  Siddhartha Panda

发明人： Zhijiong Luo ,  Hung Y. Ng ,  Nivo Rovedo ,  Phung T. Nguyen ,  William C. Wille ,  Richard Lindsay ,  Zhao Lun ,  Yung Fu Chong ,  Siddhartha Panda

IPC分类号： H01L21/76

CPC分类号： H01L21/823892 ,  H01L21/76218 ,  H01L21/76232 ,  H01L21/823878

摘要： A semiconductor structure includes a base semiconductor substrate having a doped region located therein, and an epitaxial region located over the doped region. The semiconductor structure also includes a final isolation region located with the doped region and the epitaxial region. The final isolation region has a greater linewidth within the doped region than within the epitaxial region. A method for fabricating the semiconductor structure provides for forming the doped region prior to the epitaxial region. The doped region may be formed with reduced well implant energy and reduced lateral straggle. The final isolation region with the variable linewidth provides a greater effective isolation depth than an actual trench isolation depth.

摘要翻译： 半导体结构包括具有位于其中的掺杂区的基极半导体衬底和位于掺杂区上方的外延区。 半导体结构还包括位于掺杂区和外延区的最后隔离区。 最后的隔离区域在掺杂区域内具有比外延区域内更大的线宽。 制造半导体结构的方法提供了在外延区之前形成掺杂区。 掺杂区域可以形成为具有减少的良好注入能量和减小的横向分层。 具有可变线宽的最终隔离区域提供比实际沟槽隔离深度更大的有效隔离深度。

公开(公告)号：US07785950B2

公开(公告)日：2010-08-31

申请号：US11164114

申请日：2005-11-10

申请人： Sunfei Fang ,  Jun Jung Kim ,  Zhijiong Luo ,  Hung Y. Ng ,  Nivo Rovedo ,  Young Way Teh

发明人： Sunfei Fang ,  Jun Jung Kim ,  Zhijiong Luo ,  Hung Y. Ng ,  Nivo Rovedo ,  Young Way Teh

IPC分类号： H01L21/8238 ,  H01L21/469

CPC分类号： H01L21/823864 ,  H01L21/823807

摘要： A method for providing a dual stress memory technique in a semiconductor device including an nFET and a PFET and a related structure are disclosed. One embodiment of the method includes forming a tensile stress layer over the nFET and a compressive stress layer over the pFET, annealing to memorize stress in the semiconductor device and removing the stress layers. The compressive stress layer may include a high stress silicon nitride deposited using a high density plasma (HDP) deposition method. The annealing step may include using a temperature of approximately 400-1200° C. The high stress compressive silicon nitride and/or the anneal temperatures ensure that the compressive stress memorization is retained in the pFET.

摘要翻译： 公开了一种在包括nFET和PFET以及相关结构的半导体器件中提供双重应力记忆技术的方法。 该方法的一个实施例包括在nFET上形成拉伸应力层，并在pFET上形成压应力层，退火以在半导体器件中记忆应力并去除应力层。 压应力层可以包括使用高密度等离子体（HDP）沉积方法沉积的高应力氮化硅。 退火步骤可以包括使用约400-1200℃的温度。高应力压缩氮化硅和/或退火温度确保压应力记忆保留在pFET中。

公开(公告)号：US20070267753A1

公开(公告)日：2007-11-22

申请号：US11383965

申请日：2006-05-18

申请人： Zhijiong Luo ,  Huilong Zhu ,  Yung Fu Chong ,  Hung Y. Ng ,  Kern Rim ,  Nivo Rovedo

发明人： Zhijiong Luo ,  Huilong Zhu ,  Yung Fu Chong ,  Hung Y. Ng ,  Kern Rim ,  Nivo Rovedo

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L21/823814 ,  H01L21/823871 ,  H01L21/823878 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure, semiconductor device and method having a substantially L-shaped silicide element for a contact are disclosed. The substantially L-shaped silicide element, inter alia, reduces contact resistance and may allow increased density of CMOS circuits. In one embodiment, the structure includes a substantially L-shaped silicide element including a base member and an extended member, wherein the base member extends at least partially into a shallow trench isolation (STI) region such that a substantially horizontal surface of the base member directly contacts a substantially horizontal surface of the STI region; and a contact contacting the substantially L-shaped silicide element. The contact may include a notch region for mating with the base member and a portion of the extended member, which increases the silicide-to-contact area and reduces contact resistance. Substantially L-shaped silicide element may be formed about a source/drain region, which increases the silicon-to-silicide area, and reduces crowding and contact resistance.

摘要翻译： 公开了具有用于接触的大致L形硅化物元件的结构，半导体器件和方法。 基本上L形的硅化物元件尤其降低了接触电阻并且可以允许增加的CMOS电路的密度。 在一个实施例中，该结构包括基本上为L形的硅化物元件，其包括基底构件和延伸构件，其中基底构件至少部分地延伸到浅沟槽隔离（STI）区域中，使得基底构件的基本水平的表面 直接接触STI区域的基本水平的表面; 以及接触基本上L形的硅化物元件的接触。 触点可以包括用于与基底构件和延伸构件的一部分配合的切口区域，这增加了硅化物与接触面积并降低了接触电阻。 可以围绕源极/漏极区域形成基本上L形的硅化物元素，这增加了硅 - 硅化物面积，并且减少了拥挤和接触电阻。