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6 条记录 (耗时 0.018 秒)

    N-channel MOSFETs comprising dual stressors, and methods for forming the same
    1.
    发明授权
    N-channel MOSFETs comprising dual stressors, and methods for forming the same 有权
    包含双重应力的N沟道MOSFET及其形成方法

    公开(公告)号：US07279758B1

    公开(公告)日：2007-10-09

    申请号：US11420047

    申请日：2006-05-24

    申请人： Jinghong H. Li ,  Yaocheng Liu ,  Zhijiong Luo ,  Anita Madan ,  Nivo Rovedo

    发明人： Jinghong H. Li ,  Yaocheng Liu ,  Zhijiong Luo ,  Anita Madan ,  Nivo Rovedo

    IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC分类号： H01L21/823814 ,  H01L21/26506 ,  H01L21/324 ,  H01L21/823807 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848 ,  Y10S257/90

    摘要： The present invention relates to a semiconductor device including at least one n-channel field effect transistor (n-FET). Specifically, the n-FET includes first and second patterned stressor layers that both contain a carbon-substituted and tensilely stressed single crystal semiconductor. The first patterned stressor layer has a first carbon concentration and is located in source and drain (S/D) extension regions of the n-FET at a first depth. The second patterned stressor layer has a second, higher carbon concentration and is located in S/D regions of the n-FET at a second, deeper depth. Such an n-FET with the first and second patterned stressor layers of different carbon concentration and different depths provide improved stress profile for enhancing electron mobility in the channel region of the n-FET.

    摘要翻译： 本发明涉及包括至少一个n沟道场效应晶体管（n-FET）的半导体器件。 具体地说，n-FET包括均包含碳取代和拉伸应力单晶半导体的第一和第二图案应力层。 第一图案应力层具有第一碳浓度并且位于第一深度处的n-FET的源极和漏极（S / D）延伸区域中。 第二图案应力层具有第二较高的碳浓度，并且位于第二较深深度处的n-FET的S / D区中。 这种具有不同碳浓度和不同深度的第一和第二图案应力层的n-FET提供了改善的应力分布，用于增强n-FET的沟道区域中的电子迁移率。

    N-channel MOSFETs comprising dual stressors, and methods for forming the same
    2.
    发明授权
    N-channel MOSFETs comprising dual stressors, and methods for forming the same 有权
    包含双重应力的N沟道MOSFET及其形成方法

    公开(公告)号：US07473608B2

    公开(公告)日：2009-01-06

    申请号：US11840795

    申请日：2007-08-17

    申请人： Jinghong H. Li ,  Yaocheng Liu ,  Zhijiong Luo ,  Anita Madan ,  Nivo Rovedo

    发明人： Jinghong H. Li ,  Yaocheng Liu ,  Zhijiong Luo ,  Anita Madan ,  Nivo Rovedo

    IPC分类号： H01L21/22

    CPC分类号： H01L21/823814 ,  H01L21/26506 ,  H01L21/324 ,  H01L21/823807 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848 ,  Y10S257/90

    摘要： The present invention relates to a semiconductor device comprising at least one n-channel field effect transistor (n-FET). Specifically, the n-FET comprises first and second patterned stressor layers that both contain a carbon-substituted and tensilely stressed single crystal semiconductor. The first patterned stressor layer has a first carbon concentration and is located in source and drain (S/D) extension regions of the n-FET at a first depth. The second patterned stressor layer has a second, higher carbon concentration and is located in S/D regions of the n-FET at a second, deeper depth. Such an n-FET with the first and second patterned stressor layers of different carbon concentration and different depths provide improved stress profile for enhancing electron mobility in the channel region of the n-FET.

    摘要翻译： 本发明涉及包括至少一个n沟道场效应晶体管（n-FET）的半导体器件。 具体地说，n-FET包括第一和第二图案应力层，它们都包含碳取代和拉伸应力单晶半导体。 第一图案应力层具有第一碳浓度并且位于第一深度处的n-FET的源极和漏极（S / D）延伸区域中。 第二图案应力层具有第二较高的碳浓度，并且位于第二较深深度处的n-FET的S / D区中。 这种具有不同碳浓度和不同深度的第一和第二图案应力层的n-FET提供了改善的应力分布，用于增强n-FET的沟道区域中的电子迁移率。

    Bottle-shaped trench capacitor with enhanced capacitance
    5.
    发明授权
    Bottle-shaped trench capacitor with enhanced capacitance 有权
    具有增强电容的瓶形沟槽电容器

    公开(公告)号：US08021945B2

    公开(公告)日：2011-09-20

    申请号：US12423242

    申请日：2009-04-14

    申请人： Xi Li ,  Russell H. Arndt ,  Kangguo Cheng ,  Richard O. Henry ,  Jinghong H. Li

    发明人： Xi Li ,  Russell H. Arndt ,  Kangguo Cheng ,  Richard O. Henry ,  Jinghong H. Li

    IPC分类号： H01L21/8242

    CPC分类号： H01L29/66181 ,  H01L27/10829 ,  H01L27/1087 ,  H01L28/82 ,  Y10S438/964

    摘要： In accordance with an aspect of the invention, a method is provided for fabricating a semiconductor chip including a trench capacitor. In such method, a monocrystalline semiconductor region can be etched in a vertical direction through an opening in a dielectric layer to form a trench exposing a rough surface of monocrystalline semiconductor material. The trench has an initial lateral dimension in a first direction transverse to the vertical direction. The semiconductor material exposed at the surface of the trench then is etched in a crystallographic orientation-dependent manner to expose a multiplicity of crystal facets of the semiconductor material at the trench surface. A dopant-containing liner may then be deposited to line the surface of the trench and a temperature of the substrate then be elevated to drive a dopant from the dopant-containing liner into the semiconductor region adjacent to the surface. During such step, typically a portion of the semiconductor material exposed at the wall is oxidized. At least some of the oxidized portion is removed to expose a wall of an enlarged trench, along which wall a dielectric layer and conductive material are formed in order to form a trench capacitor.

    摘要翻译： 根据本发明的一个方面，提供一种用于制造包括沟槽电容器的半导体芯片的方法。 在这种方法中，可以通过电介质层中的开口在垂直方向上蚀刻单晶半导体区域，以形成露出单晶半导体材料的粗糙表面的沟槽。 沟槽在垂直于垂直方向的第一方向上具有初始侧向尺寸。 然后在晶体表面上暴露的半导体材料以结晶方向依赖的方式进行蚀刻，以在沟槽表面暴露半导体材料的多个晶面。 然后可以沉积含掺杂剂的衬里以对沟槽的表面进行排列，然后升高衬底的温度以将掺杂剂从含掺杂剂的衬里驱动到与表面相邻的半导体区域中。 在这样的步骤中，通常暴露在壁处的半导体材料的一部分被氧化。 去除至少一些氧化部分以露出扩大的沟槽的壁，沿着该壁形成介电层和导电材料以形成沟槽电容器。

    BOTTLE-SHAPED TRENCH CAPACITOR WITH ENHANCED CAPACITANCE
    6.
    发明申请
    BOTTLE-SHAPED TRENCH CAPACITOR WITH ENHANCED CAPACITANCE 有权
    具有增强电容的瓶形TRENCH电容器

    公开(公告)号：US20100258904A1

    公开(公告)日：2010-10-14

    申请号：US12423242

    申请日：2009-04-14

    申请人： Xi Li ,  Russell H. Arndt ,  Kangguo Cheng ,  Richard O. Henry ,  Jinghong H. Li

    发明人： Xi Li ,  Russell H. Arndt ,  Kangguo Cheng ,  Richard O. Henry ,  Jinghong H. Li

    IPC分类号： H01L27/07 ,  H01L21/02

    CPC分类号： H01L29/66181 ,  H01L27/10829 ,  H01L27/1087 ,  H01L28/82 ,  Y10S438/964

    摘要： In accordance with an aspect of the invention, a method is provided for fabricating a semiconductor chip including a trench capacitor. In such method, a monocrystalline semiconductor region can be etched in a vertical direction through an opening in a dielectric layer to form a trench exposing a rough surface of monocrystalline semiconductor material. The trench has an initial lateral dimension in a first direction transverse to the vertical direction. The semiconductor material exposed at the surface of the trench then is etched in a crystallographic orientation-dependent manner to expose a multiplicity of crystal facets of the semiconductor material at the trench surface. A dopant-containing liner may then be deposited to line the surface of the trench and a temperature of the substrate then be elevated to drive a dopant from the dopant-containing liner into the semiconductor region adjacent to the surface. During such step, typically a portion of the semiconductor material exposed at the wall is oxidized. At least some of the oxidized portion is removed to expose a wall of an enlarged trench, along which wall a dielectric layer and conductive material are formed in order to form a trench capacitor.

    摘要翻译： 根据本发明的一个方面，提供一种用于制造包括沟槽电容器的半导体芯片的方法。 在这种方法中，可以通过电介质层中的开口在垂直方向上蚀刻单晶半导体区域，以形成露出单晶半导体材料的粗糙表面的沟槽。 沟槽在垂直于垂直方向的第一方向上具有初始侧向尺寸。 然后在晶体表面上暴露的半导体材料以结晶方向依赖的方式进行蚀刻，以在沟槽表面暴露半导体材料的多个晶面。 然后可以沉积含掺杂剂的衬里以对沟槽的表面进行排列，然后升高衬底的温度以将掺杂剂从含掺杂剂的衬里驱动到与表面相邻的半导体区域中。 在这样的步骤中，通常暴露在壁处的半导体材料的一部分被氧化。 去除至少一些氧化部分以露出扩大的沟槽的壁，沿着该壁形成介电层和导电材料以形成沟槽电容器。