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    Electrically programmable memory cell configuration
    1.
    发明授权
    Electrically programmable memory cell configuration 失效
    电可编程存储单元配置

    公开(公告)号：US6118159A

    公开(公告)日：2000-09-12

    申请号：US259376

    申请日：1999-02-26

    申请人： Josef Willer ,  Franz Hofmann ,  Hans Reisinger ,  Emmerich Bertagnolli ,  Bernd Gobel ,  Barbara Hasler ,  Karl-Heinz Tietgen

    发明人： Josef Willer ,  Franz Hofmann ,  Hans Reisinger ,  Emmerich Bertagnolli ,  Bernd Gobel ,  Barbara Hasler ,  Karl-Heinz Tietgen

    IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/76 ,  H01L29/788

    CPC分类号： H01L27/11517 ,  H01L27/115

    摘要： The memory cell configuration comprises vertical transistors which are connected in a NOR architecture. The vertical transistors are disposed on flanks of trenches. Each vertical transistor includes an electrically insulated floating gate electrode, whose charge can be varied by Fowler-Nordheim tunneling due to a voltage drop between a control gate electrode and a source/drain region. The length of a coupling area in a direction parallel to a channel width, between the control gate electrode and the floating gate electrode is less than the channel width, in order to reduce the operating voltage. This is achieved by thermal oxidation of parts of the flanks of the trenches. Transistors which are adjacent in a direction transverse to the trenches share bit lines. Each bit line has a lightly doped first part and a highly doped second part. The coupling area can be enlarged even further by using a strip-shaped mask, which is extended by spacers.

    摘要翻译： 存储单元配置包括以NOR架构连接的垂直晶体管。 垂直晶体管设置在沟槽的侧面。 每个垂直晶体管包括电绝缘浮栅，其电荷可以由于控制栅极电极和源极/漏极区域之间的压降而由Fowler-Nordheim隧穿而改变。 为了降低工作电压，与控制栅电极和浮置栅电极之间的通道宽度平行的方向上的耦合区域的长度小于沟道宽度。 这是通过沟槽侧面部分的热氧化实现的。 在横向于沟槽的方向上相邻的晶体管共享位线。 每个位线具有轻掺杂的第一部分和高度掺杂的第二部分。 通过使用由间隔物延伸的带状掩模，可以进一步扩大耦合面积。

    SRAM cell arrangement and method for manufacturing same
    2.
    发明授权
    SRAM cell arrangement and method for manufacturing same 有权
    SRAM单元布置及其制造方法

    公开(公告)号：US06222753B1

    公开(公告)日：2001-04-24

    申请号：US09446419

    申请日：1999-12-20

    申请人： Bernd Goebel ,  Emmerich Bertagnolli ,  Josef Willer ,  Barbara Hasler ,  Paul-Werner von Basse

    发明人： Bernd Goebel ,  Emmerich Bertagnolli ,  Josef Willer ,  Barbara Hasler ,  Paul-Werner von Basse

    IPC分类号： G11C700

    CPC分类号： H01L27/11 ,  H01L27/1104

    摘要： An SRAM cell arrangement which includes six MOS transistors per memory cell wherein each transistor is formed as a vertical transistors. The MOS transistors are arranged at sidewalls of trenches. Parts of the memory cell such as, for example, gate electrodes or conductive structures fashioned as spacers are contacted via adjacent, horizontal, conductive structures arranged above a surface of a substrate. Connections between parts of memory cells occur via third conductive structures arranged at the sidewalls of the depressions and word lines via diffusion regions that are adjacent to the sidewalls of the depressions within the substrate, via first bit lines, via second bit lines and/or via conductive structures that are partially arranged at different heights with respect to an axis perpendicular to the surface. Contacts contact a plurality of parts of the MOS transistors simultaneously.

    摘要翻译： 每个存储单元包括六个MOS晶体管的SRAM单元布置，其中每个晶体管形成为垂直晶体管。 MOS晶体管布置在沟槽的侧壁。 存储单元的部分，例如栅极电极或形成为间隔物的导电结构，经由布置在衬底表面上方的相邻的水平导电结构接触。 存储器单元的部分之间的连接通过布置在凹陷和字线的侧壁处的第三导电结构经由第一位线经由第二位线和/或通孔的扩散区域经由衬底内的凹陷的侧壁相邻布置 相对于垂直于表面的轴部分地布置在不同高度的导电结构。 触头同时接触MOS晶体管的多个部分。

    SRAM cell arrangement and method for manufacturing same
    3.
    发明授权
    SRAM cell arrangement and method for manufacturing same 有权
    SRAM单元布置及其制造方法

    公开(公告)号：US06309930B1

    公开(公告)日：2001-10-30

    申请号：US09708636

    申请日：2000-11-09

    申请人： Bernd Goebel ,  Emmerich Bertagnolli ,  Josef Willer ,  Barbara Hasler ,  Paul-Werner von Basse

    发明人： Bernd Goebel ,  Emmerich Bertagnolli ,  Josef Willer ,  Barbara Hasler ,  Paul-Werner von Basse

    IPC分类号： H01L21336

    CPC分类号： H01L27/11 ,  H01L27/1104

    摘要： The SRAM cell arrangement comprises six MOS transistors per memory cell that are fashioned as vertical transistors. The MOS transistors are arranged at sidewalls of trenches (G1, G2, G4). Parts of the memory cell such as, for example, gate electrodes (Ga2, Ga4) or conductive structures (L3) fashioned as spacer are contacted via adjacent, horizontal, conductive structures (H5) arranged above a surface (O) of a substrate (S). Connections between parts of memory cells ensue via third conductive structures (L3) arranged at the sidewalls of the depressions and word lines (W) via diffusion regions (D2) that are adjacent to the sidewalls of the depressions within the substrate (S), via first bit lines, via second bit lines (B2) or/and via conductive structures (L1, L2, L6) that are partially arranged at different height with respect to an axis perpendicular to the surface (O). Contacts (K5) contact a plurality of parts of the MOS transistors simultaneously.

    摘要翻译： SRAM单元布置包括每个存储单元的六个MOS晶体管，其被形成为垂直晶体管。 MOS晶体管布置在沟槽（G1，G2，G4）的侧壁处。 诸如例如形成隔离物的栅极（Ga2，Ga4）或导电结构（L3）的存储单元的部分通过布置在衬底的表面（O）上方的相邻的水平导电结构（H5）接触 S）。 存储器单元的部分之间的连接经由经由扩散区（D2）布置在凹陷和字线（W）的侧壁处的第三导电结构（L3），其经由衬底（S）内的凹陷的侧壁相邻的经由 通过相对于垂直于表面（O）的轴线以不同高度部分布置的第二位线（B2）或/和经由导电结构（L1，L2，L6）的第一位线。 触点（K5）同时接触MOS晶体管的多个部分。

    Method of operating a storage cell arrangement
    4.
    发明授权
    Method of operating a storage cell arrangement 失效
    操作存储单元布置的方法

    公开(公告)号：US6040995A

    公开(公告)日：2000-03-21

    申请号：US230614

    申请日：1999-01-28

    申请人： Hans Reisinger ,  Ulrike Gruning ,  Hermann Wendt ,  Reinhard Stengl ,  Volker Lehmann ,  Josef Willer ,  Martin Franosch ,  Herbert Schafer ,  Wolfgang Krautschneider ,  Franz Hofmann ,  Thomas Bohm

    发明人： Hans Reisinger ,  Ulrike Gruning ,  Hermann Wendt ,  Reinhard Stengl ,  Volker Lehmann ,  Josef Willer ,  Martin Franosch ,  Herbert Schafer ,  Wolfgang Krautschneider ,  Franz Hofmann ,  Thomas Bohm

    IPC分类号： H01L21/8247 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792 ,  H01L27/02

    CPC分类号： H01L29/513 ,  H01L29/518 ,  H01L29/792

    摘要： For the operation of a memory cell arrangement with MOS transistors as memory cells that comprise a dielectric triple layer (5) with a first silicon oxide layer (51), a silicon nitride layer (52) and a second silicon oxide layer (53) as gate dielectric, whereby the silicon oxide layers are respectively at least 3 nm thick, a first cutoff voltage value is allocated to a first logical value and a second cutoff voltage value of the MOS transistor is allocated to a second logical value for storing digital data. The information stored in the memory cell can be modified by applying corresponding voltage levels, although a complete removal of charge stored in the silicon nitride layer is not possible because of the thickness of the silicon oxide layers. What is exploited when modifying the cutoff voltage is that the electrical field in the dielectric triple layer is distorted by charge stored in the silicon nitride layer.

    摘要翻译： PCT No.PCT / DE97 / 01601 Sec。 371日期1999年1月28日 102（e）1999年1月28日PCT PCT 1997年7月29日PCT公布。 出版物WO98 / 06140 日期1998年2月12日对于具有MOS晶体管的存储单元布置的操作，作为包含具有第一氧化硅层（51）的介电三层（5）的存储单元，具有氮化硅层（52）和第二氧化硅 层（53）作为栅极电介质，由此氧化硅层​​分别为至少3nm厚，将第一截止电压值分配给第一逻辑值，并将MOS晶体管的第二截止电压值分配给第二逻辑值 用于存储数字数据。 存储在存储单元中的信息可以通过施加相应的电压电平来修改，尽管由于氧化硅层的厚度，不可能完全去除存储在氮化硅层中的电荷。 当修改截止电压时，利用的是电介质三层中的电场由存储在氮化硅层中的电荷而失真。

    Method for manufacturing an electrically writeable and erasable read-only memory cell arrangement
    5.
    发明授权
    Method for manufacturing an electrically writeable and erasable read-only memory cell arrangement 失效
    用于制造电可写和可擦除的只读存储单元布置的方法

    公开(公告)号：US5882969A

    公开(公告)日：1999-03-16

    申请号：US967419

    申请日：1997-11-11

    申请人： Wolfgang Krautschneider ,  Franz Hofmann ,  Hans Reisinger ,  Josef Willer

    发明人： Wolfgang Krautschneider ,  Franz Hofmann ,  Hans Reisinger ,  Josef Willer

    IPC分类号： H01L21/822 ,  H01L21/8247 ,  H01L29/788 ,  H01L29/792 ,  H01L21/336 ,  H01L29/78

    CPC分类号： H01L27/11521 ,  H01L21/8221 ,  H01L27/11551

    摘要： In a method for manufacturing an electrically writeable and erasable ad-only memory cell arrangement, by self-adjusting process steps, a read-only memory cell arrangement having memory cells that respectively comprise an MOS transistor with a floating gate is manufactured. The MOS transistors are arranged in rows that run parallel. Adjacent rows thus respectively run alternately on the bottom of longitudinal trenches and between adjacent longitudinal trenches. The control gates laterally surround the floating gates so that the memory cells on the bottom of the longitudinal trenches also comprise a coupling ratio>1. A surface requirement per memory cell of 2F.sup.2 (F minimum structural size) is achieved.

    摘要翻译： 在通过自调整处理步骤制造电可写和可擦除的仅ad的存储单元布置的方法中，制造了具有分别包括具有浮置栅极的MOS晶体管的存储单元的只读存储单元布置。 MOS晶体管排列成并行的行。 因此，相邻的行分别在纵向沟槽的底部和相邻的纵向沟槽之间交替地行进。 控制门横向围绕浮动栅极，使得纵向沟槽底部的存储单元也包括耦合比> 1。 实现2F2（F最小结构尺寸）每个存储单元的表面要求。

    Electrically programmable memory cell array, using charge carrier traps and insulation trenches
    7.
    发明授权
    Electrically programmable memory cell array, using charge carrier traps and insulation trenches 失效
    电可编程存储单元阵列，使用电荷载流子阱和绝缘沟槽

    公开(公告)号：US06191459B1

    公开(公告)日：2001-02-20

    申请号：US08780488

    申请日：1997-01-08

    申请人： Franz Hofmann ,  Wolfgang Krautschneider ,  Josef Willer ,  Hans Reisinger

    发明人： Franz Hofmann ,  Wolfgang Krautschneider ,  Josef Willer ,  Hans Reisinger

    IPC分类号： H01L2976

    CPC分类号： H01L29/7926 ,  H01L27/115 ,  H01L27/11556 ,  H01L29/792

    摘要： An electrically programmable memory cell array is formed of memory cells, which include a vertical MOS transistor. The MOS transistor has a gate dielectric of a material with charge carrier traps. The memory cells are disposed along opposite edges of striplike, parallel insulation trenches. The width and spacing of the insulation trenches are preferably identical. The space required per memory cell of the memory cell array is 2F2, where F is the minimum structural size in the technology employed. The memory cells are programmed by selectively injecting electrons into the gate dielectric.

    摘要翻译： 电可编程存储单元阵列由包括垂直MOS晶体管的存储单元形成。 MOS晶体管具有具有电荷载流子阱的材料的栅极电介质。 存储单元沿带状平行绝缘沟槽的相对边缘设置。 绝缘沟槽的宽度和间距优选相同。 存储单元阵列每个存储单元所需的空间为2F2，其中F为所采用技术中的最小结构尺寸。 通过选择性地将电子注入到栅极电介质中来对存储器单元进行编程。

    Method for the manufacturing a memory cell configuration
    8.
    发明授权
    Method for the manufacturing a memory cell configuration 失效
    制造存储单元配置的方法

    公开(公告)号：US6153475A

    公开(公告)日：2000-11-28

    申请号：US331495

    申请日：1999-06-21

    申请人： Franz Hofmann ,  Josef Willer ,  Hans Reisinger ,  Wolfgang Krautschneider ,  Paul-Werner von Basse

    发明人： Franz Hofmann ,  Josef Willer ,  Hans Reisinger ,  Wolfgang Krautschneider ,  Paul-Werner von Basse

    IPC分类号： H01L21/8246 ,  H01L27/112 ,  H01L21/336

    CPC分类号： H01L27/112

    摘要： For the manufacture of a memory cell arrangement with first memory cells that comprise a vertical MOS transistor and with second memory cells that do not comprise an MOS transistor, whereby the memory cells are arranged along opposite edges of strip-type trenches, memory cells that are adjacent along the trenches (5) are manufactured successively. The spacing of adjacent memory cells is determined in particular by means of a spacer technology. By this means, a space requirement per memory cell of 1F.sup.2 can be realized, whereby F is the minimum structural size of the respective technology.

    摘要翻译： PCT No.PCT / DE97 / 02549 Sec。 371 1999年6月21日第 102（e）日期1999年6月21日PCT 1997年11月4日PCT PCT。 第WO98 / 27586号公报 日期1998年6月25日为了制造具有包括垂直MOS晶体管的第一存储单元和不包括MOS晶体管的第二存储单元的存储单元布置，由此存储单元沿带状沟槽的相对边缘布置 沿着沟槽（5）相邻的存储单元依次制造。 特别是通过间隔物技术来确定相邻存储单元的间隔。 通过这种方式，可以实现1F2的每个存储单元的空间要求，由此F是相应技术的最小结构尺寸。