公开(公告)号：US5572704A

公开(公告)日：1996-11-05

申请号：US167005

申请日：1993-12-15

申请人： Joseph P. Bratt ,  John Brennan ,  Peter Y. Hsu ,  William A. Huffman ,  Joseph T. Scanlon ,  Steve Ciavagia

发明人： Joseph P. Bratt ,  John Brennan ,  Peter Y. Hsu ,  William A. Huffman ,  Joseph T. Scanlon ,  Steve Ciavagia

IPC分类号： G06F12/08 ,  G06F12/16

CPC分类号： G06F12/0811

摘要： A method for preventing data loss and deadlock in a multi-processor computer system wherein at least one processor in the computer system includes a split-level cache. The split-level cache has a byte-writable first-level and a word-writable second level. The method monitors the second level cache to determine if a forced atomic (FA) instruction is in a second level cache pipeline. If an FA instruction is determined to be in the second level cache pipeline, then interventions to the second level cache are delayed until the FA instruction exits the second level cache pipeline. In this manner data written by operation of cache memory access instruction that cause the interventions is not destroyed by the execution of the FA instruction, thereby preventing data loss. The method also monitors the second level cache pipeline to determine if a possible miss (PM) instruction is in the second level cache pipeline. If a PM instruction is determined to be in the second level cache pipeline, the FA instructions are prevented from entering the second level cache pipeline such that execution of interventions to the second level cache is not prevented when an instruction in the second level cache may be detained to process an intervention in its behalf, thereby preventing deadlock between processing units of the computer system.

摘要翻译： 一种用于在多处理器计算机系统中防止数据丢失和死锁的方法，其中所述计算机系统中的至少一个处理器包括分级高速缓存。 分级缓存具有可写字节的第一级和可写字的第二级。 该方法监视第二级高速缓存以确定强制原子（FA）指令是否在二级高速缓存流水线中。 如果FA指令被确定在第二级高速缓存流水线中，则延迟到第二级高速缓存的干预，直到FA指令退出第二级高速缓存流水线。 以这种方式，通过执行FA指令不会破坏导致干预的高速缓冲存储器访问指令的操作所写入的数据，从而防止数据丢失。 该方法还监视第二级高速缓存流水线以确定可能的未命中（PM）指令是否在第二级高速缓存流水线中。 如果确定PM指令处于第二级高速缓存流水线中，则FA指令被阻止进入第二级高速缓存流水线，使得当第二级高速缓存中的指令可能为 被拘留以代表其进行干预，从而防止计算机系统的处理单元之间的僵局。

公开(公告)号：US5537538A

公开(公告)日：1996-07-16

申请号：US166969

申请日：1993-12-15

申请人： Joseph P. Bratt ,  John Brennan ,  Peter Y. Hsu ,  Chandra S. Joshi ,  William A. Huffman ,  Monica R. Nofal ,  Paul Rodman ,  Joseph T. Scanlon ,  Man K. Tang

发明人： Joseph P. Bratt ,  John Brennan ,  Peter Y. Hsu ,  Chandra S. Joshi ,  William A. Huffman ,  Monica R. Nofal ,  Paul Rodman ,  Joseph T. Scanlon ,  Man K. Tang

IPC分类号： D06M13/46 ,  C11D1/04 ,  C11D1/62 ,  C11D1/645 ,  C11D1/65 ,  C11D1/72 ,  C11D1/835 ,  C11D3/00 ,  D06M20060101 ,  D06M13/02 ,  D06M13/184 ,  D06M13/188 ,  D06M13/322 ,  D06M13/463 ,  G06F9/38 ,  G06F11/36 ,  G06F11/34 ,  G06F9/30

CPC分类号： G06F11/3664 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3857 ,  G06F9/3861 ,  G06F9/3867 ,  G06F9/3885

摘要： A processor system that is switchable between a normal mode of operation without precise floating point exceptions and a debug mode of operation with precise floating point exceptions. The processor system includes a dispatch for dispatching integer and floating point instructions, an integer unit having a multi-stage integer pipeline for executing the integer instructions, and a floating point unit having a multi-stage floating point pipeline for executing the floating point instructions. The system begins operation in the normal mode, and upon receipt of an instruction to "switch to debug mode," the processor switches to the debug mode of operation with precise exceptions. In the debug mode, once a floating point instruction has been dispatched, all other instructions are prevented from being committed until the system determines whether the floating point instruction generates an exception. Thus, permitting the system to signal precise exceptions when not in the normal mode.

摘要翻译： 处理器系统，可在正常操作模式之间切换，无需精确的浮点异常，以及具有精确浮点异常的调试操作模式。 处理器系统包括调度整数和浮点指令的调度，具有用于执行整数指令的多级整数流水线的整数单元，以及具有用于执行浮点指令的多级浮点流水线的浮点单元。 系统在正常模式下开始运行，并且在接收到“切换到调试模式”的指令时，处理器切换到调试操作模式，具有精确的例外。 在调试模式下，一旦调度了浮点指令，就会阻止所有其他指令被提交，直到系统确定浮点指令是否产生异常。 因此，允许系统在不处于正常模式时发出精确异常。

公开(公告)号：US5632025A

公开(公告)日：1997-05-20

申请号：US696788

申请日：1996-08-14

申请人： Joseph P. Bratt ,  John Brennan ,  Peter Y. T. Hsu ,  William A. Huffman ,  Joseph T. Scanlon ,  Steve Ciavaglia

发明人： Joseph P. Bratt ,  John Brennan ,  Peter Y. T. Hsu ,  William A. Huffman ,  Joseph T. Scanlon ,  Steve Ciavaglia

IPC分类号： G06F12/08 ,  G06F12/14

CPC分类号： G06F12/0811

摘要： A method for preventing deadlock due to the need for data exclusivity when performing forced atomic instructions in a multi-level cache in a multi-processor system. The system determines whether an aligned multi-byte word in which the data of a forced atomic instruction, such as an integer store operation, is exclusive in a first level cache. If so, the forced atomic instruction is allowed to enter a second level cache pipeline. If not, the forced atomic instruction is prevented from entering the second level cache pipeline and a cache miss and fill operation is initiated to cause the aligned word to be exclusive in the first level cache.

摘要翻译： 一种用于在多处理器系统中的多级缓存中执行强制原子指令时由于需要数据排他性而防止死锁的方法。 系统确定其中诸如整数存储操作的强制原子指令的数据在第一级高速缓存中是否排他的对齐的多字节字。 如果是这样，则强制原子指令被允许进入第二级高速缓存流水线。 如果不是，则强制原子指令被阻止进入第二级高速缓存流水线并且启动高速缓存未命中和填充操作以使对齐的字在第一级高速缓存中是排他的。

公开(公告)号：US5740402A

公开(公告)日：1998-04-14

申请号：US487240

申请日：1995-06-13

申请人： Joseph P. Bratt ,  John Brennen ,  Peter Y. Hsu ,  Joseph T. Scanlon ,  Man Kit Tang ,  Steven J. Ciavaglia

发明人： Joseph P. Bratt ,  John Brennen ,  Peter Y. Hsu ,  Joseph T. Scanlon ,  Man Kit Tang ,  Steven J. Ciavaglia

IPC分类号： G06F12/06 ,  G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0851 ,  G06F12/0607

摘要： A conflict resolution system for interleaved memories in processors capable of issuing multiple independent memory operations per cycle. The conflict resolution system includes an address bellow for temporarily storing memory requests, and cross-connect switches to variously route multiple parallel memory requests to multiple memory banks. A control logic block controls the address bellow and the cross-connect switches to reorder the sequence of memory requests to avoid conflicts. The reordering removes conflicts and increases the occurrence of alternating memory requests that can issue simultaneously.

摘要翻译： 用于处理器中的交错存储器的冲突解决系统，其能够在每个周期发出多个独立的存储器操作。 冲突解决系统包括用于临时存储存储器请求的地址，以及交叉连接交换机以将多个并行存储器请求不同地路由到多个存储体。 控制逻辑块控制下面的地址和交叉连接交换机重新排序存储器请求的顺序以避免冲突。 重新排序会消除冲突并增加可同时发出的交替内存请求的发生。

公开(公告)号：US08749568B2

公开(公告)日：2014-06-10

申请号：US12685166

申请日：2010-01-11

申请人： Joseph P. Bratt ,  Shing Choo ,  Peter F. Holland ,  Timothy J. Millet

发明人： Joseph P. Bratt ,  Shing Choo ,  Peter F. Holland ,  Timothy J. Millet

IPC分类号： G09G5/36

CPC分类号： G06T1/60 ,  G09G5/14 ,  G09G5/363 ,  G09G2340/10 ,  G09G2360/12 ,  G09G2360/127

摘要： A graphics system may include one or more processing units for processing a current display frame, each processing unit including a plurality of parameter registers for storing parameter settings used in processing the current display frame. A parameter buffer in the graphics system may store frame packets, with each frame packet containing information corresponding to parameter settings to be used for at least one display frame. A control circuit coupled to the buffer and to the one or more processing units may retrieve and process a top frame packet from the parameter buffer to update one or more of the parameter registers according to the contents of the top frame packet. The control circuit may issue DMA requests to fill the parameter buffer with frame packets transferred from system memory, where the frame packets may be written by an application (or software) executing on a central processing unit.

公开(公告)号：US08749565B2

公开(公告)日：2014-06-10

申请号：US12950239

申请日：2010-11-19

申请人： Joseph P. Bratt ,  Peter F. Holland ,  David L. Bowman

发明人： Joseph P. Bratt ,  Peter F. Holland ,  David L. Bowman

IPC分类号： G06T1/60

CPC分类号： G09G5/397 ,  G09G5/36 ,  G09G2330/12 ,  G09G2340/0407 ,  G09G2340/06 ,  G09G2340/10 ,  G09G2340/125 ,  G09G2360/10 ,  G09G2360/125

摘要： Video display pipes may terminate with a FIFO (first-in first-out) buffer from which pixels are provided to a display controller to display the pixels on a graphics/video display. The display pipes may frequently process the pixels at a much higher rate than at which the display controller fetches the pixels from the FIFO buffer. In an error-checking only mode, the FIFO may be disabled, and an error-checking (e.g. CRC) block connected in front of the FIFO may receive the pixels processed by the display pipes as fast as the display pipes are capable of processing the pixels. Accordingly, the length of test/simulation time required to perform a test may be determined by the rate at which pixels are generated rather than the rate at which the display controller displays the pixels. It also becomes possible to perform testing/simulation in environments where a display is not supported or is not available. The results generated by the error-checking may be read and compared to an expected value to detect test pass/fail conditions.

摘要翻译： 视频显示管道可以用FIFO（先进先出）缓冲器终止，从而将像素提供给显示控制器以在图形/视频显示器上显示像素。 显示管道可以以比显示控制器从FIFO缓冲器提取像素的速率高得多的速率来频繁地处理像素。 在仅错误检查模式中，FIFO可以被禁用，并且连接在FIFO前面的错误校验（例如CRC）块可以像显示管能够处理显示管一样快地接收由显示管处理的像素 像素。 因此，执行测试所需的测试/模拟时间的长度可以由生成像素的速率而不是显示控制器显示像素的速率来确定。 在不支持显示或不可用的环境中也可以进行测试/模拟。 可以读取错误检查产生的结果并将其与期望值进行比较，以检测测试通过/失败条件。

公开(公告)号：US08711170B2

公开(公告)日：2014-04-29

申请号：US13026559

申请日：2011-02-14

申请人： Joseph P. Bratt ,  Peter F. Holland ,  Gokhan Avkarogullari

发明人： Joseph P. Bratt ,  Peter F. Holland ,  Gokhan Avkarogullari

IPC分类号： G09G5/02

CPC分类号： G06T15/005 ,  G06T13/80 ,  G06T15/503

摘要： A video display pipe used for processing pixels of video and/or image frames may include edge Alpha registers for storing edge Alpha values corresponding to the edges of an image to be translated across a display screen. The edge Alpha values may be specified based on the fractional pixel value by which the image is to be moved in the current frame. The video pipe may copy the column and row of pixels that are in the direction of travel, and may apply the edge Alpha values to the copied column and row. The edge Alpha values may control blending of the additional column and row of the translated image with the adjacent pixels in the original frame, providing the effect of the partial pixel movement, simulating a sub-pixel rate of movement.

摘要翻译： 用于处理视频和/或图像帧的像素的视频显示管可以包括边缘Alpha寄存器，用于存储与通过显示屏幕翻译的图像的边缘相对应的边缘α值。 可以基于在当前帧中移动图像的分数像素值来指定边缘Alpha值。 视频管道可以复制行进方向的像素列和行，并且可以将边缘Alpha值应用于复制的列和行。 边缘Alpha值可以控制翻转图像的附加列和行与原始帧中的相邻像素的混合，从而提供部分像素移动的效果，模拟子像素移动速率。

公开(公告)号：US08493482B2

公开(公告)日：2013-07-23

申请号：US12858922

申请日：2010-08-18

申请人： Guy Cote ,  Jeffrey E. Frederiksen ,  Joseph P. Bratt ,  Shun Wai Go ,  Timothy J. Millet

发明人： Guy Cote ,  Jeffrey E. Frederiksen ,  Joseph P. Bratt ,  Shun Wai Go ,  Timothy J. Millet

IPC分类号： H04N3/14 ,  H04N5/335 ,  H01L31/062

CPC分类号： H04N5/232 ,  H04N5/2258 ,  H04N5/23245

摘要： Various techniques are provided for processing image data acquired using a digital image sensor. In accordance with aspects of the present disclosure, one such technique may relate to the processing of image data in a system that supports multiple image sensors. In one embodiment, the image processing system may include control circuitry configured to determine whether a device is operating in a single sensor mode (one active sensor) or a dual sensor mode (two active sensors). When operating in the single sensor mode, data may be provided directly to a front-end pixel processing unit from the sensor interface of the active sensor. When operating in a dual sensor mode, the image frames from the first and second sensors are provided to the front-end pixel processing unit in an interleaved manner. For instance, in one embodiment, the image frames from the first and second sensors are written to a memory, and then read out to the front-end pixel processing unit in an interleaved manner.

摘要翻译： 提供了用于处理使用数字图像传感器获取的图像数据的各种技术。 根据本公开的方面，一种这样的技术可以涉及在支持多个图像传感器的系统中对图像数据的处理。 在一个实施例中，图像处理系统可以包括被配置为确定设备是以单个传感器模式（一个有源传感器）或双传感器模式（两个有源传感器）操作的控制电路。 当在单传感器模式下操作时，数据可以从有源传感器的传感器接口直接提供给前端像素处理单元。 当以双传感器模式操作时，来自第一和第二传感器的图像帧以交错的方式提供给前端像素处理单元。 例如，在一个实施例中，来自第一和第二传感器的图像帧被写入存储器，然后以交错的方式读出到前端像素处理单元。

公开(公告)号：US20120206657A1

公开(公告)日：2012-08-16

申请号：US13026557

申请日：2011-02-14

申请人： Joseph P. Bratt ,  Peter F. Holland

发明人： Joseph P. Bratt ,  Peter F. Holland

IPC分类号： H04N9/64

CPC分类号： H04N9/646 ,  G06F7/584 ,  G09G2320/0271

摘要： A display pipe unit for processing pixels of video and/or image frames may be injected with dither-noise during processing of the pixels. A random noise generator implemented using Linear Feedback Shift Registers (LFSRs) produces pseudo-random numbers that are injected into the display pipe as dither-noise. Typically, such LFSRs shift freely during operation and the values of the LFSRs are used as needed. By shifting the LFSRs when the values are used to inject noise into newly received data, and not shifting the LFSRs when no new data is received, variations in the delays of receiving the data do not affect the pattern of noise applied to the frames. Therefore, dither-noise can be deterministically injected into the display pipe during testing/debug operation. By updating the LFSRs when new pixel data is available from the host interface instead of updating the LFSRs every cycle, the same dither-noise can be injected for the same received data.

摘要翻译： 用于处理视频和/或图像帧的像素的显示管单元可以在处理像素期间被注入抖动噪声。 使用线性反馈移位寄存器（LFSR）实现的随机噪声发生器产生作为抖动噪声注入显示管道的伪随机数。 通常，这样的LFSR在操作期间自由移动，并且根据需要使用LFSR的值。 当使用这些值将噪声注入到新接收到的数据中时，通过移位LFSR，并且在没有接收到新数据时不移动LFSR，接收数据的延迟的变化不影响施加到帧的噪声模式。 因此，在测试/调试操作期间，可以将抖动噪声确定性地注入显示管道。 当从主机接口获得新像素数据而不是每个周期更新LFSR时，通过更新LFSR，可以为相同的接收数据注入相同的抖动噪声。

公开(公告)号：US20120206468A1

公开(公告)日：2012-08-16

申请号：US13026559

申请日：2011-02-14

申请人： Joseph P. Bratt ,  Peter F. Holland ,  Gokhan Avkarogullari

发明人： Joseph P. Bratt ,  Peter F. Holland ,  Gokhan Avkarogullari

IPC分类号： G09G5/36

CPC分类号： G06T15/005 ,  G06T13/80 ,  G06T15/503

摘要： A video display pipe used for processing pixels of video and/or image frames may include edge Alpha registers for storing edge Alpha values corresponding to the edges of an image to be translated across a display screen. The edge Alpha values may be specified based on the fractional pixel value by which the image is to be moved in the current frame. The video pipe may copy the column and row of pixels that are in the direction of travel, and may apply the edge Alpha values to the copied column and row. The edge Alpha values may control blending of the additional column and row of the translated image with the adjacent pixels in the original frame, providing the effect of the partial pixel movement, simulating a sub-pixel rate of movement.

摘要翻译： 用于处理视频和/或图像帧的像素的视频显示管可以包括边缘Alpha寄存器，用于存储与通过显示屏幕翻译的图像的边缘相对应的边缘α值。 可以基于在当前帧中移动图像的分数像素值来指定边缘Alpha值。 视频管道可以复制行进方向的像素列和行，并且可以将边缘Alpha值应用于复制的列和行。 边缘Alpha值可以控制翻转图像的附加列和行与原始帧中的相邻像素的混合，从而提供部分像素移动的效果，模拟子像素移动速率。