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    INFORMATION PROCESSING APPARATUS AND INFORMATION PROCESSING METHOD
    1.
    发明公开
    INFORMATION PROCESSING APPARATUS AND INFORMATION PROCESSING METHOD 审中-公开

    公开(公告)号：US20240103470A1

    公开(公告)日：2024-03-28

    申请号：US18456209

    申请日：2023-08-25

    Applicant: Kioxia Corporation

    Inventor： Yuma YOSHINAGA ,  Atsushi MAESONO ,  Osamu TORII ,  Shinichiro TOMIOKA ,  Shinichiro MANABE

    IPC: G05B19/042

    CPC classification number: G05B19/042

    Abstract: An information processing apparatus that updates a regression coefficient parameter based on a predetermined objective function including a regularization term for each of a plurality of elements characterized by a task and a feature value, the information processing apparatus comprising processing circuitry. The processing circuitry selects an element which is an update target of the regression coefficient parameter from the plurality of elements, fixes a value of the regularization term of an unselected element, selects a calculation expression for updating a regression coefficient parameter of the selected element based on a regression coefficient parameter of the unselected element, and updates the regression coefficient parameter of the selected element based on the selected calculation expression.

    SEMICONDUCTOR MEMORY DEVICE TO HOLD 5-BITS OF DATA PER MEMORY CELL
    2.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE TO HOLD 5-BITS OF DATA PER MEMORY CELL 有权

    公开(公告)号：US20220270678A1

    公开(公告)日：2022-08-25

    申请号：US17738069

    申请日：2022-05-06

    Applicant: KIOXIA CORPORATION

    Inventor： Tomonori TAKAHASHI ,  Masanobu SHIRAKAWA ,  Osamu TORII ,  Marie TAKADA

    IPC: G11C11/56 ,  G11C16/26 ,  G11C16/08 ,  G11C16/04

    Abstract: According to one embodiment, a semiconductor memory device includes: a memory cell configured to hold 5-bit data; a word line coupled to the memory cell; and a row decoder configured to apply first to 31st voltages to the word line. A first bit of the 5-bit data is established by reading operations using first to sixth voltages. A second bit of the 5-bit data is established by reading operations using seventh to twelfth voltages. A third bit of the 5-bit data is established by reading operations using thirteenth to eighteenth voltages. A fourth bit of the 5-bit data is established by reading operations using nineteenth to 25th voltages. A fifth bit of the 5-bit data is established by reading operations using 26th to 31st voltages.

    INFORMATION PROCESSING APPARATUS AND INFORMATION PROCESSING METHOD
    4.
    发明公开
    INFORMATION PROCESSING APPARATUS AND INFORMATION PROCESSING METHOD 审中-公开

    公开(公告)号：US20240095306A1

    公开(公告)日：2024-03-21

    申请号：US18453105

    申请日：2023-08-21

    Applicant: Kioxia Corporation

    Inventor： Osamu TORII ,  Shinichiro MANABE

    IPC: G06F17/18

    CPC classification number: G06F17/18

    Abstract: An information processing apparatus comprising processing circuitry. The processing circuitry is configured to acquire objective variables and explanatory variables which are regression analysis targets, extract a plurality of first explanatory variables having a high degree of influence on the objective variable from among the explanatory variables by sparse modeling using a first regression equation, and extract a second explanatory variable having a high degree of influence on the plurality of first explanatory variables by sparse modeling using a second regression equation.

    MEMORY SYSTEM
    8.
    发明申请
    MEMORY SYSTEM 有权

    公开(公告)号：US20210279133A1

    公开(公告)日：2021-09-09

    申请号：US17184166

    申请日：2021-02-24

    Applicant: Kioxia Corporation

    Inventor： Yuma YOSHINAGA ,  Tomoya KODAMA ,  Osamu TORII ,  Kenichiro FURUTA ,  Ryota YOSHIZAWA

    IPC: G06F11/10 ,  H03M13/45 ,  G06N3/04 ,  G06N3/08

    Abstract: A memory system includes a non-volatile memory and a memory controller. The memory controller is configured to read a received word from the non-volatile memory, estimate noise by using a plurality of different models for estimating the noise included in the received word to obtain a plurality of noise estimation values, select one noise estimation value from the plurality of noise estimation values, update the received word by using a value obtained by subtracting the selected noise estimation value from the read received word, and decode the updated received word by using a belief-propagation method.

    LEARNING DEVICE
    9.
    发明申请
    LEARNING DEVICE 有权

    公开(公告)号：US20210242888A1

    公开(公告)日：2021-08-05

    申请号：US17005270

    申请日：2020-08-27

    Applicant: KIOXIA CORPORATION

    Inventor： Ryota YOSHIZAWA ,  Kenichiro FURUTA ,  Yuma YOSHINAGA ,  Osamu TORII ,  Tomoya KODAMA

    IPC: H03M13/29 ,  H03M13/45 ,  G06N3/08

    Abstract: According to one embodiment, a learning device includes a noise generation unit, a decoding unit, a generation unit, and a learning unit. The noise generation unit outputs a second code word which corresponds to a first code word to which noise has been added. The decoding unit decodes the second code word and outputs a third code word. The generation unit generates learning data for learning a weight in message passing decoding in which the weight and a message to be transmitted are multiplied, based on whether or not decoding of the second code word into the third code word has been successful. The learning unit determines a value for the weight in the message passing decoding by using the learning data.

    MEMORY SYSTEM
    10.
    发明申请
    MEMORY SYSTEM 有权

    公开(公告)号：US20210089392A1

    公开(公告)日：2021-03-25

    申请号：US16807220

    申请日：2020-03-03

    Applicant: Kioxia Corporation

    Inventor： Masanobu SHIRAKAWA ,  Hideki YAMADA ,  Marie TAKADA ,  Ryo YAMAKI ,  Osamu TORII ,  Naomi TAKEDA

    IPC: G06F11/10 ,  G06F9/30

    Abstract: According to one embodiment, a memory system controls a shift resister memory and writes encoded data including a plurality of error correction code frames into a block of the shift resister memory. The memory system is configured to store, into a location corresponding to a first layer in a first data storing shift string, first data included in a first error correction code frame, to store, into a location corresponding to a second layer in the first data storing shift string, second data included in a second error correction code frame, and to store, into a location corresponding to the second layer in a second data storing shift string, third data included in the first error correction code frame.

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