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    MEMORY SYSTEM
    1.
    发明公开
    MEMORY SYSTEM 审中-公开

    公开(公告)号：US20230297239A1

    公开(公告)日：2023-09-21

    申请号：US17898370

    申请日：2022-08-29

    Applicant: KIOXIA CORPORATION

    Inventor： Kenta SHIBASAKI ,  Yoshihiko SHINDO ,  Yasuhiro HIRASHIMA ,  Akio SUGAHARA ,  Shigeki NAGASAKA ,  Dai NAKAMURA ,  Yousuke HAGIWARA

    IPC: G06F3/06

    CPC classification number: G06F3/0613 ,  G06F3/0679 ,  G06F3/0653

    Abstract: A memory system includes a memory chip and a memory controller. The memory chip includes a storage region that stores setup data used for setup of the memory chip during power on thereof. The memory controller is configured to determine whether or not the memory controller has the setup data, when determining that the memory controller does not have the setup data, instruct the memory chip to read the setup data from the storage region and perform a first setup operation based on the read setup data, and when determining that the memory controller has the setup data, transmit the setup data to the memory chip and instruct the memory chip to perform a second setup operation based on the setup data received from the memory controller.

    SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM
    2.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM 审中-公开

    公开(公告)号：US20230213993A1

    公开(公告)日：2023-07-06

    申请号：US18181488

    申请日：2023-03-09

    Applicant: Kioxia Corporation

    Inventor： Akio SUGAHARA ,  Yasuhiro HIRASHIMA ,  Naoya TOKIWA

    IPC: G06F1/28

    CPC classification number: G06F1/28 ,  G11C16/0483

    Abstract: According to an embodiment, a semiconductor memory device includes a first pin, a first receiving circuit, and a first terminating circuit. The first pin receives a first signal and a second signal having a smaller amplitude than the first signal. The first receiving circuit is connected to the first pin and outputs, based on a comparison between the first signal and a first voltage, a third signal. The first receiving circuit also outputs, based on a comparison between the second signal and a second voltage, a fourth signal having a smaller amplitude than the third signal. The first terminating circuit is connected to the first pin. The first terminating circuit is disabled if the first pin receives the first signal, and enabled if the first pin receives the second signal.

    SEMICONDUCTOR DEVICE
    3.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20230188137A1

    公开(公告)日：2023-06-15

    申请号：US18165195

    申请日：2023-02-06

    Applicant: Kioxia Corporation

    Inventor： Yasuhiro HIRASHIMA ,  Masaru KOYANAGI ,  Yutaka TAKAYAMA

    IPC: H03K19/0175 ,  H01L23/538

    CPC classification number: H03K19/017509 ,  H01L23/5384

    Abstract: A semiconductor device includes a latch circuit including a first inverter configured to output a first signal based on an input signal, a second inverter configured to output a first clock signal based on a first strobe signal, a third inverter configured to output a second clock signal based on a second strobe signal, a first clock generation circuit configured to generate a third clock signal having transitions that are delayed with respect to the first clock signal, a second clock generation circuit configured to generate a fourth clock signal having transitions that are delayed with respect to the second clock signal, a fourth inverter configured to output an inversion signal of the first signal in accordance with the third and fourth clock signals, and a data latch circuit configured to latch an output signal of the fourth inverter.

    SEMICONDUCTOR MEMORY DEVICE
    4.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20220230665A1

    公开(公告)日：2022-07-21

    申请号：US17716295

    申请日：2022-04-08

    Applicant: Kioxia Corporation

    Inventor： Yasuhiro HIRASHIMA ,  Mitsuhiro ABE ,  Norichika ASAOKA

    IPC: G11C7/10 ,  G11C29/12

    Abstract: According to one embodiment, a semiconductor memory device includes: a first delay circuit configured to delay a first signal and provide a variable delay time; a first select circuit configured to select a second signal or a third signal based on the first signal delayed by the first delay circuit; a first output buffer configured to output a fourth signal based on a signal selected by the first select circuit; a first output pad configured to externally output the fourth signal; and a counter configured to count a number of times the fourth signal is output.

    SEMICONDUCTOR MEMORY DEVICE
    6.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20230078945A1

    公开(公告)日：2023-03-16

    申请号：US17681592

    申请日：2022-02-25

    Applicant: KIOXIA CORPORATION

    Inventor： Yasuhiro HIRASHIMA

    IPC: G11C7/10 ,  G11C8/06

    Abstract: A semiconductor memory device includes a memory cell array, first and second pads, an interface circuit connected to the first pad and configured to transmit data input through the first pad to the memory cell array and output data received from the memory cell array through the first pad, a ZQ calibration circuit that is connected to the second pad and executes a ZQ calibration to generate a ZQ calibration value, and a sequencer configured to control the ZQ calibration circuit to apply the ZQ calibration value to the interface circuit. A command set is input through the first pad after reading data from the memory cell array to cause the interface circuit to output the data read from the memory cell array, and the ZQ calibration circuit executes the ZQ calibration after the command set is input and before the data is output through the first pad.

    SEMICONDUCTOR INTEGRATED CIRCUIT AND SEMICONDUCTOR STORAGE DEVICE
    7.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT AND SEMICONDUCTOR STORAGE DEVICE 有权

    公开(公告)号：US20210295930A1

    公开(公告)日：2021-09-23

    申请号：US17118703

    申请日：2020-12-11

    Applicant: Kioxia Corporation

    Inventor： Fumiya WATANABE ,  Masaru KOYANAGI ,  Yutaka SHIMIZU ,  Yasuhiro HIRASHIMA ,  Kei SHIRAISHI ,  Mikihiko ITO

    IPC: G11C16/32 ,  G11C7/10 ,  G11C16/10

    Abstract: According to one embodiment, in a semiconductor integrated circuit, an input circuit has an input and an output stage electrically connected to the input stage via a first node and a second node. The input stage includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first time constant adjusting circuit and a second time constant adjusting circuit. The first transistor has a gate that receives an input signal. The second transistor has a gate that receives a reference signal. The third transistor is disposed adjacent to a drain of the first transistor. The fourth transistor is disposed adjacent to a drain of the second transistor. The first time constant adjusting circuit is electrically connected between a gate of the third transistor and the first node. The second time constant adjusting circuit is electrically connected between a gate of the fourth transistor and the second node.

    SEMICONDUCTOR INTEGRATED CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE
    8.
    发明公开
    SEMICONDUCTOR INTEGRATED CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20240195372A1

    公开(公告)日：2024-06-13

    申请号：US18489140

    申请日：2023-10-18

    Applicant: Kioxia Corporation

    Inventor： Yutaka SHIMIZU ,  Yasuhiro HIRASHIMA ,  Isao FUJISAWA ,  Michael BURGHART ,  Yuanlun ZHANG

    IPC: H03F3/45 ,  H10B41/30 ,  H10B43/30

    CPC classification number: H03F3/45659 ,  H10B41/30 ,  H10B43/30 ,  H03F2203/45091

    Abstract: An amplifier of an input circuit includes: a first PMOS transistor having a gate connected to a first node, a source connected to a second node, and a drain connected to a third node; a second PMOS transistor having a gate connected to a fourth node that inputs a reference signal, a source connected to the second node, and a drain connected to a fifth node; a current source connected between a power supply voltage and the second node; a load circuit connected between the third node and a ground voltage; a first NMOS transistor having a gate connected to the first node, a drain connected to the power supply voltage, and a source connected to the fifth node; and a second NMOS transistor having a gate connected to the fourth node, a drain connected to the power supply voltage, and a source connected to the third node.

    SEMICONDUCTOR DEVICE
    9.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20210409023A1

    公开(公告)日：2021-12-30

    申请号：US17473012

    申请日：2021-09-13

    Applicant: KIOXIA CORPORATION

    Inventor： Yasuhiro HIRASHIMA ,  Masaru KOYANAGI ,  Yutaka TAKAYAMA

    IPC: H03K19/0175 ,  H01L23/538

    Abstract: A semiconductor device includes a latch circuit including a first inverter configured to output a first signal based on an input signal, a second inverter configured to output a first clock signal based on a first strobe signal, a third inverter configured to output a second clock signal based on a second strobe signal, a first clock generation circuit configured to generate a third clock signal having transitions that are delayed with respect to the first clock signal, a second clock generation circuit configured to generate a fourth clock signal having transitions that are delayed with respect to the second clock signal, a fourth inverter configured to output an inversion signal of the first signal in accordance with the third and fourth clock signals, and a data latch circuit configured to latch an output signal of the fourth inverter.

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