-
1.发明授权公开(公告)号：US11761880B2
公开(公告)日：2023-09-19
申请号：US16531940
申请日：2019-08-05
Applicant: KLA-Tencor Corporation
Inventor： Pradeep Vukkadala , Haiguang Chen , Jaydeep K. Sinha , Sathish Veeraraghavan
CPC classification number: G01N19/08 , C23C14/54 , G01L1/00 , G01L5/0047 , G03F7/705 , G03F7/70633 , G03F7/70783 , H01L22/12 , H01L22/20
Abstract: Systems and methods for prediction and measurement of overlay errors are disclosed. Process-induced overlay errors may be predicted or measured utilizing film force based computational mechanics models. More specifically, information with respect to the distribution of film force is provided to a finite element (FE) model to provide more accurate point-by-point predictions in cases where complex stress patterns are present. Enhanced prediction and measurement of wafer geometry induced overlay errors are also disclosed.
-
2.发明授权公开(公告)号：US10401279B2
公开(公告)日：2019-09-03
申请号：US14490408
申请日：2014-09-18
Applicant: KLA-Tencor Corporation
Inventor： Pradeep Vukkadala , Haiguang Chen , Jaydeep Sinha , Sathish Veeraraghavan
Abstract: Systems and methods for prediction and measurement of overlay errors are disclosed. Process-induced overlay errors may be predicted or measured utilizing film force based computational mechanics models. More specifically, information with respect to the distribution of film force is provided to a finite element (FE) model to provide more accurate point-by-point predictions in cases where complex stress patterns are present. Enhanced prediction and measurement of wafer geometry induced overlay errors are also disclosed.
-
公开(公告)号：US10249523B2
公开(公告)日：2019-04-02
申请号：US15135022
申请日：2016-04-21
Applicant: KLA-Tencor Corporation
Inventor： Pradeep Vukkadala , Sathish Veeraraghavan , Jaydeep K. Sinha
Abstract: The present invention may include acquiring a wafer shape value at a plurality of points of a wafer surface at a first and second process level, generating a wafer shape change value at each of the points, generating a set of slope of shape change values at each of the points, calculating a set of process tool correctables utilizing the generated set of slope of shape change values, generating a set of slope shape change residuals (SSCRs) by calculating a slope of shape change residual value at each of the points utilizing the set of process tool correctables, defining a plurality of metric analysis regions distributed across the surface, and then generating one or more residual slope shape change metrics for each metric analysis region based on one or more SSCRs within each metric analysis region.
-
4.发明申请公开(公告)号：US20160372353A1
公开(公告)日：2016-12-22
申请号：US15135022
申请日：2016-04-21
Applicant: KLA-Tencor Corporation
Inventor： Pradeep Vukkadala , Sathish Veeraraghavan , Jaydeep K. Sinha
CPC classification number: H01L21/67288 , G01B9/02021 , G01B9/02027 , G01B9/02057 , G01B11/161 , G01B11/2441 , G01B11/272 , G03F7/70633 , G03F7/70783 , H01L21/67271 , H01L22/12 , H01L2924/0002 , H01L2924/00
Abstract: The present invention may include acquiring a wafer shape value at a plurality of points of a wafer surface at a first and second process level, generating a wafer shape change value at each of the points, generating a set of slope of shape change values at each of the points, calculating a set of process tool correctables utilizing the generated set of slope of shape change values, generating a set of slope shape change residuals (SSCRs) by calculating a slope of shape change residual value at each of the points utilizing the set of process tool correctables, defining a plurality of metric analysis regions distributed across the surface, and then generating one or more residual slope shape change metrics for each metric analysis region based on one or more SSCRs within each metric analysis region.
Abstract translation: 本发明可以包括在第一和第二处理水平的晶片表面的多个点处获取晶片形状值，在每个点产生晶片形状变化值，在每个点产生一组形状变化值的斜率 使用所生成的形状变化值的斜率来计算一组处理工具可校正性，通过使用该集合计算每个点处的形状变化残差值的斜率，生成一组斜率变化残差（SSCR） 定义过程表面上分布的多个度量分析区域，然后基于每个度量分析区域内的一个或多个SSCR，为每个度量分析区域生成一个或多个残留斜率形状变化度量。
-
5.发明申请Enhanced Inspection and Metrology Techniques And Systems Using Bright-Field Differential Interference Contrast 有权增强的检测和计量技术和使用明场差分干涉对比的系统公开(公告)号：US20140268172A1
公开(公告)日：2014-09-18
申请号：US13797901
申请日：2013-03-12
Applicant: KLA-Tencor Corporation
Inventor： Ali Salehpour , Jaydeep Sinha , Kurt Lindsay Haller , Pradeep Vukkadala , George Kren , Jiayao Zhang , Mehdi Vaez-Iravani
IPC: G01B11/24
CPC classification number: G01B11/303 , G01B11/306 , G01B2210/56
Abstract: A method of providing high accuracy inspection or metrology in a bright-field differential interference contrast (BF-DIC) system is described. This method can include creating first and second beams from a first light beam. The first and second beams have round cross-sections, and form first partially overlapping scanning spots radially displaced on a substrate. Third and fourth beams are created from the first light beam or a second light beam. The third and fourth beams have elliptical cross-sections, and form second partially overlapping scanning spots tangentially displaced on the substrate. At least one portion of the substrate can be scanned using the first and second partially overlapping scanning spots as the substrate is rotated. Radial and tangential slopes can be determined using measurements obtained from the scanning using the first and second partially overlapping scanning spots. These slopes can be used to determine wafer shape or any localized topography feature.
Abstract translation: 描述了在亮场差分干涉对比（BF-DIC）系统中提供高精度检测或计量的方法。 该方法可以包括从第一光束产生第一和第二光束。 第一和第二光束具有圆形横截面，并形成在衬底上径向位移的第一部分重叠的扫描点。 从第一光束或第二光束产生第三和第四光束。 第三和第四光束具有椭圆形横截面，并形成在衬底上切向位移的第二部分重叠的扫描点。 当衬底旋转时，可以使用第一和第二部分重叠的扫描点来扫描衬底的至少一部分。 可以使用从使用第一和第二部分重叠的扫描点的扫描获得的测量来确定径向和切向斜率。 这些斜面可用于确定晶片形状或任何局部地形特征。
-
Patent Agency Ranking
6.发明申请Systems, Methods and Metrics for Wafer High Order Shape Characterization and Wafer Classification Using Wafer Dimensional Geometry Tool 有权使用晶圆尺寸几何工具的晶圆高阶形状表征和晶圆分类的系统，方法和度量公开(公告)号：US20140114597A1
公开(公告)日：2014-04-24
申请号：US13656143
申请日：2012-10-19
Applicant: KLA-Tencor Corporation
Inventor： Haiguang Chen , Jaydeep Sinha , Sergey Kamensky , Sathish Veeraraghavan , Pradeep Vukkadala
CPC classification number: G01B11/24 , G01B2210/56 , G01N21/9501 , G06F17/00 , H01L22/12
Abstract: Systems and methods for improving results of wafer higher order shape (HOS) characterization and wafer classification are disclosed. The systems and methods in accordance with the present disclosure are based on localized shapes. A wafer map is partitioned into a plurality of measurement sites to improve the completeness of wafer shape representation. Various site based HOS metric values may be calculated for wafer characterization and/or classification purposes, and may also be utilized as control input for a downstream application. In addition, polar grid partitioning schemes are provided. Such polar grid partitioning schemes may be utilized to partition a wafer surface into measurement sites having uniform site areas while providing good wafer edge region coverage.
Abstract translation: 公开了用于改善晶片高阶形状（HOS）表征和晶片分类的结果的系统和方法。 根据本公开的系统和方法基于局部形状。 将晶片图划分成多个测量点，以提高晶片形状表示的完整性。 可以针对晶片表征和/或分类目的计算各种基于站点的HOS度量值，并且还可以用作下游应用的控制输入。 此外，还提供了极坐标分割方案。 可以利用这种极性栅格划分方案将晶片表面划分成具有均匀位置区域的测量位置，同时提供良好的晶片边缘区域覆盖。
-
公开(公告)号：US11164768B2
公开(公告)日：2021-11-02
申请号：US16019341
申请日：2018-06-26
Applicant: KLA-Tencor Corporation
Inventor： Pradeep Vukkadala , Mark D. Smith , Ady Levy , Prasanna Dighe , Dieter Mueller
Abstract: A controller is configured to perform at least a first characterization process prior to at least one discrete backside film deposition process on a semiconductor wafer; perform at least an additional characterization process following the at least one discrete backside film deposition process; determine at least one of a film force or one or more in-plane displacements for at least one discrete backside film deposited on the semiconductor wafer via the at least one discrete backside film deposition process based on the at least the first characterization process and the at least the additional characterization process; and provide at least one of the film force or the one or more in-plane displacements to at least one process tool via at least one of a feed forward loop or a feedback loop to improve performance of one or more fabrication processes.
-
公开(公告)号：US20190271654A1
公开(公告)日：2019-09-05
申请号：US15406732
申请日：2017-01-15
Applicant: KLA-Tencor Corporation
Inventor： Haiguang Chen , Jaydeep Sinha , Sergey Kamensky , Sathish Veeraraghavan , Pradeep Vukkadala
Abstract: Systems and methods for improving results of wafer higher order shape (HOS) characterization and wafer classification are disclosed. The systems and methods in accordance with the present disclosure are based on localized shapes. A wafer map is partitioned into a plurality of measurement sites to improve the completeness of wafer shape representation. Various site based HOS metric values may be calculated for wafer characterization and/or classification purposes, and may also be utilized as control input for a downstream application. In addition, polar grid partitioning schemes are provided. Such polar grid partitioning schemes may be utilized to partition a wafer surface into measurement sites having uniform site areas while providing good wafer edge region coverage.
-
公开(公告)号：US10025894B2
公开(公告)日：2018-07-17
申请号：US15172667
申请日：2016-06-03
Applicant: KLA-Tencor Corporation
Inventor： Pradeep Vukkadala , Sathish Veeraraghavan , Jaydeep Sinha , Haiguang Chen , Michael Kirk
Abstract: Systems and methods for prediction of in-plane distortions (IPD) due to wafer shape in semiconductor wafer chucking process is disclosed. A series of Zernike basis wafer shapes process to emulate the non-linear finite element (FE) contact mechanics model based IPD prediction is utilized in accordance with one embodiment of the present disclosure. The emulated FE model based prediction process is substantially more efficient and provides accuracy comparable to the FE model based IPD prediction that utilizes full-scale 3-D wafer and chuck geometry information and requires computation intensive simulations. Furthermore, an enhanced HOS IPD/OPD prediction process based on a series of Zernike basis wafer shape images is also disclosed.
-
10.发明授权公开(公告)号：US09779202B2
公开(公告)日：2017-10-03
申请号：US14867226
申请日：2015-09-28
Applicant: KLA-Tencor Corporation
Inventor： Pradeep Vukkadala , Jaydeep Sinha , Jong-Hoon Kim
CPC classification number: G06F17/5081 , G03F1/44 , G03F7/705 , G03F7/70633 , G06F17/5068 , G06F2217/12 , Y02P90/265
Abstract: Systems and methods to detect, quantify, and control process-induced asymmetric signatures using patterned wafer geometry measurements are disclosed. The system may include a geometry measurement tool configured to obtain a first set of wafer geometry measurements of the wafer prior to the wafer undergoing a fabrication process and to obtain a second set of wafer geometry measurements of the wafer after the fabrication process. The system may also include a processor in communication with the geometry measurement tool. The processor may be configured to: calculate a geometry-change map based on the first set of wafer geometry measurements and the second set of wafer geometry measurements; analyze the geometry-change map to detect an asymmetric component induced to wafer geometry by the fabrication process; and estimate an asymmetric overlay error induced by the fabrication process based on the asymmetric component detected in wafer geometry.
-
-
-
-
-
-
-
-
-
Search Results
38
records
(took 0.019 seconds)
