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公开(公告)号：US07491994B2
公开(公告)日：2009-02-17
申请号：US11216387
申请日：2005-08-31
IPC分类号： H01L29/94
CPC分类号： G11C11/15 , H01L27/1203 , H01L43/065
摘要： In a first aspect, a first apparatus is provided. The first apparatus is a memory cell that includes (1) a semiconductor fin enclosure formed on an insulating layer of a substrate; and (2) a ferromagnetic material within the semiconductor fin enclosure. A top surface of the ferromagnetic material is below a top surface of the semiconductor fin enclosure. Numerous other aspects are provided.
摘要翻译： 在第一方面中，提供了一种第一装置。 第一装置是存储单元，其包括：（1）形成在基板的绝缘层上的半导体翅片外壳; 和（2）半导体翅片外壳内的铁磁材料。 铁磁材料的顶表面位于半导体翅片外壳的顶表面之下。 提供了许多其他方面。
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2.发明授权Structures incorporating semiconductor device structures with reduced junction capacitance and drain induced barrier lowering 有权结合了具有减小的结电容和漏极引起的屏障降低的半导体器件结构公开(公告)号：US07984408B2
公开(公告)日：2011-07-19
申请号：US11875013
申请日：2007-10-19
CPC分类号： H01L29/78603 , G11C29/54 , H01L29/51 , H01L29/513 , H01L29/66545 , H01L29/66636 , H01L29/66772
摘要： Design structure embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes semiconductor device structures characterized by reduced junction capacitance and drain induced barrier lowering. The semiconductor device structure of the design structure includes a semiconductor layer and a dielectric layer disposed between the semiconductor layer and the substrate. The dielectric layer includes a first dielectric region with a first dielectric constant and a second dielectric region with a second dielectric constant that is greater than the first dielectric constant.
摘要翻译： 用于设计，制造或测试设计的机器可读介质中体现的设计结构。 该设计结构包括半导体器件结构，其特征在于结电容减小和漏极引起的栅极降低。 设计结构的半导体器件结构包括设置在半导体层和衬底之间的半导体层和介电层。 电介质层包括具有第一介电常数的第一电介质区域和具有大于第一介电常数的第二介电常数的第二电介质区域。
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公开(公告)号：US20090007036A1
公开(公告)日：2009-01-01
申请号：US11925387
申请日：2007-10-26
IPC分类号： G06F9/45
CPC分类号： H01L21/845 , H01L27/1211 , H01L29/41791 , H01L29/66795 , H01L29/785 , H01L2029/7858
摘要： Embodiments of the invention generally relate to methods, systems and design structures for semiconductor devices, and more specifically to interconnecting semiconductor devices. A silicide layer may be formed on selective areas of a fin structure connecting one or more semiconductor devices or semiconductor device components. By providing silicided fin structures to locally interconnect semiconductor devices, the use of metal contacts and metal layers may be obviated, thereby allowing formation of smaller, less complex circuits.
摘要翻译： 本发明的实施例一般涉及半导体器件的方法，系统和设计结构，更具体地涉及互连半导体器件。 可以在连接一个或多个半导体器件或半导体器件部件的翅片结构的选择性区域上形成硅化物层。 通过提供硅化物翅片结构来局部互连半导体器件，可以避免使用金属触点和金属层，从而形成较小的，较不复杂的电路。
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4.发明申请Hybrid Field Effect Transistor and Bipolar Junction Transistor Structures and Methods for Fabricating Such Structures 审中-公开混合场效应晶体管和双极结晶体管结构和制造这种结构的方法公开(公告)号：US20080001234A1
公开(公告)日：2008-01-03
申请号：US11427962
申请日：2006-06-30
IPC分类号： H01L29/76
CPC分类号： H01L29/732 , H01L21/8249 , H01L21/84 , H01L27/0623 , H01L27/12 , H01L29/66265 , H01L29/785
摘要： Semiconductor device structures that integrate field effect transistors and bipolar junction transistors on a single substrate, such as a semiconductor-on-insulator substrate, and methods for fabricating such hybrid semiconductor device structures. The field effect and bipolar junction transistors are fabricated using adjacent electrically-isolated semiconductor bodies. During fabrication of the device structures, certain fabrication stages strategically rely on block masks for process isolation. Other fabrication stages are shared during the fabrication process for seamless integration that reduces process complexity.
摘要翻译： 在诸如绝缘体上半导体衬底的单个衬底上集成场效应晶体管和双极结型晶体管的半导体器件结构以及用于制造这种混合半导体器件结构的方法。 使用相邻的电隔离半导体器件制造场效应和双极结晶体管。 在器件结构的制造过程中，某些制造阶段有策略地依靠块掩模来进行过程隔离。 其他制造阶段在无缝集成的制造过程中共享，从而降低了工艺复杂性。
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5.发明授权Semiconductor device structures with self-aligned doped regions and methods for forming such semiconductor device structures 失效具有自对准掺杂区域的半导体器件结构和用于形成这种半导体器件结构的方法公开(公告)号：US07898014B2
公开(公告)日：2011-03-01
申请号：US11393142
申请日：2006-03-30
IPC分类号： H01L27/108
CPC分类号： H01L27/10841 , H01L27/10864
摘要： Semiconductor device structures with self-aligned doped regions and methods for forming such semiconductor device structures. The semiconductor structure comprises first and second doped regions of a first conductivity type defined in the semiconductor material of a substrate bordering a sidewall of a trench. An intervening region of the semiconductor material separates the first and second doped regions. A third doped region is defined in the semiconductor material bordering the sidewall of the trench and disposed between the first and second doped regions. The third doped region is doped to have a second conductivity type opposite to the first conductivity type. Methods for forming the doped regions involve depositing either a layer of a material doped with both dopants or different layers each doped with one of the dopants in the trench and, then, diffusing the dopants from the layer or layers into the semiconductor material bordering the trench sidewall.
摘要翻译： 具有自对准掺杂区域的半导体器件结构和用于形成这种半导体器件结构的方法。 半导体结构包括限定在与沟槽的侧壁相邻的衬底的半导体材料中的第一导电类型的第一和第二掺杂区域。 半导体材料的中间区域分离第一和第二掺杂区域。 第三掺杂区域限定在与沟槽的侧壁接壤并且设置在第一和第二掺杂区域之间的半导体材料中。 第三掺杂区被掺杂以具有与第一导电类型相反的第二导电类型。 用于形成掺杂区域的方法包括沉积掺杂有掺杂剂或不同层的材料的层，每个掺杂剂或不同的层在沟槽中掺杂有一种掺杂剂，然后将掺杂剂从层或层扩散到与沟槽接壤的半导体材料 侧壁。
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6.发明授权Reduced-resistance finFETs by sidewall silicidation and methods of manufacturing the same 有权通过侧壁硅化物的降低电阻finFET及其制造方法公开(公告)号：US07531423B2
公开(公告)日：2009-05-12
申请号：US11316244
申请日：2005-12-22
IPC分类号： H01L21/76
CPC分类号： H01L29/785 , H01L21/823418 , H01L21/823437 , H01L29/41791 , H01L29/665 , H01L29/6653 , H01L29/66795 , H01L29/78618 , H01L2029/7858 , Y10S438/96
摘要： In a first aspect, a first method of manufacturing a finFET is provided. The first method includes the steps of (1) providing a substrate; and (2) forming at least one source/drain diffusion region of the finFET on the substrate. Each source/drain diffusion region includes (a) an interior region of unsilicided silicon; and (b) silicide formed on a top surface and sidewalls of the region of unsilicided silicon. Numerous other aspects are provided.
摘要翻译： 在第一方面，提供了制造finFET的第一种方法。 第一种方法包括以下步骤：（1）提供衬底; 和（2）在所述衬底上形成所述finFET的至少一个源极/漏极扩散区域。 每个源极/漏极扩散区域包括（a）非硅化硅的内部区域; 和（b）硅化物形成在非硅化硅区域的顶表面和侧壁上。 提供了许多其他方面。
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7.发明申请SEMICONDUCTOR DEVICE STRUCTURES FOR BIPOLAR JUNCTION TRANSISTORS AND METHODS OF FABRICATING SUCH STRUCTURES 失效双极晶体管的半导体器件结构和制作这种结构的方法公开(公告)号：US20080220583A1
公开(公告)日：2008-09-11
申请号：US12125342
申请日：2008-05-22
IPC分类号： H01L21/331
CPC分类号： H01L29/732 , H01L29/66265
摘要： Semiconductor device structures for use with bipolar junction transistors and methods of fabricating such semiconductor device structures. The semiconductor device structure comprises a semiconductor body having a top surface and sidewalls extending from the top surface to an insulating layer, a first region including a first semiconductor material with a first conductivity type, and a second region including a second semiconductor material with a second conductivity type. The first and second regions each extend across the top surface and the sidewalls of the semiconductor body. The device structure further comprises a junction defined between the first and second regions and extending across the top surface and the sidewalls of the semiconductor body.
摘要翻译： 用于双极结晶体管的半导体器件结构和制造这种半导体器件结构的方法。 半导体器件结构包括具有顶表面和从顶表面延伸到绝缘层的侧壁的半导体本体，包括具有第一导电类型的第一半导体材料的第一区域和包括具有第二导电类型的第二半导体材料的第二区域 导电类型。 第一和第二区域各自延伸穿过半导体本体的顶表面和侧壁。 器件结构还包括限定在第一和第二区域之间并且跨越半导体本体的顶表面和侧壁延伸的接合部。
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8.发明申请Method for Reducing Defects in Buried Oxide Layers of Silicon on Insulator Substrates 审中-公开减少硅绝缘体衬底氧化层缺陷的方法公开(公告)号：US20080048259A1
公开(公告)日：2008-02-28
申请号：US11466480
申请日：2006-08-23
IPC分类号： H01L27/12
CPC分类号： H01L29/78603 , H01L29/66772 , H01L29/78609
摘要： A method and a structure for reducing defects in buried oxide layers of a silicon-on-insulator substrate. The method includes: generating a beam of infrared radiation of a selected wavelength; exposing a silicon-on-insulator substrate to the beam of infrared radiation, the substrate comprising a buried silicon dioxide layer between a lower layer of silicon and an upper layer of silicon; and wherein silicon has a transmittance of at least 95% at the selected wavelength and silicon dioxide has a transmittance of less than 80% at the selected wavelength.
摘要翻译： 一种减少绝缘体上硅衬底的掩埋氧化物层缺陷的方法和结构。 该方法包括：产生所选波长的红外辐射束; 将绝缘体上硅衬底暴露于所述红外辐射束，所述衬底包括在下层硅和硅上层之间的掩埋二氧化硅层; 并且其中硅在所选波长处具有至少95％的透射率，并且二氧化硅在所选择的波长处具有小于80％的透射率。
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9.发明申请Semiconductor Device Structures for Bipolar Junction Transistors and Methods of Fabricating Such Structures 有权用于双极结晶体管的半导体器件结构和制造这种结构的方法公开(公告)号：US20080003757A1
公开(公告)日：2008-01-03
申请号：US11427982
申请日：2006-06-30
IPC分类号： H01L21/331
CPC分类号： H01L29/732 , H01L29/66265
摘要： Semiconductor device structures for use with bipolar junction transistors and methods of fabricating such semiconductor device structures. The semiconductor device structure comprises a semiconductor body having a top surface and sidewalls extending from the top surface to an insulating layer, a first region including a first semiconductor material with a first conductivity type, and a second region including a second semiconductor material with a second conductivity type. The first and second regions each extend across the top surface and the sidewalls of the semiconductor body. The device structure further comprises a junction defined between the first and second regions and extending across the top surface and the sidewalls of the semiconductor body.
摘要翻译： 用于双极结晶体管的半导体器件结构和制造这种半导体器件结构的方法。 半导体器件结构包括具有顶表面和从顶表面延伸到绝缘层的侧壁的半导体本体，包括具有第一导电类型的第一半导体材料的第一区域和包括具有第二导电类型的第二半导体材料的第二区域 导电类型。 第一和第二区域各自延伸穿过半导体本体的顶表面和侧壁。 器件结构还包括限定在第一和第二区域之间并且跨越半导体本体的顶表面和侧壁延伸的接合部。
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10.发明授权Semiconductor device structures with reduced junction capacitance and drain induced barrier lowering and methods for fabricating such device structures and for fabricating a semiconductor-on-insulator substrate 失效具有减小的结电容和漏极引起的屏障降低的半导体器件结构以及用于制造这种器件结构和用于制造绝缘体上半导体衬底的方法公开(公告)号：US07659178B2
公开(公告)日：2010-02-09
申请号：US11379655
申请日：2006-04-21
IPC分类号： H01L21/311 , H01L21/3115
CPC分类号： H01L29/66545 , H01L29/51 , H01L29/513 , H01L29/66636 , H01L29/66772 , H01L29/78603 , Y10S438/96
摘要： Semiconductor device structures with reduced junction capacitance and drain induced barrier lowering, methods for fabricating such device structures, and methods for forming a semiconductor-on-insulator substrate. The semiconductor structure comprises a semiconductor layer and a dielectric layer disposed between the semiconductor layer and the substrate. The dielectric layer includes a first dielectric region with a first dielectric constant and a second dielectric region with a second dielectric constant that is greater than the first dielectric constant. In one embodiment, the dielectric constant of the first dielectric region may be less than about 3.9 and the dielectric constant of the second dielectric region may be greater than about ten (10). The semiconductor-on-insulator substrate comprises a semiconductor layer separated from a bulk layer by an insulator layer of a high-dielectric constant material. The fabrication methods comprise modifying a region of the dielectric layer to have a lower dielectric constant.
摘要翻译： 具有减小的结电容和漏极引发的屏障降低的半导体器件结构，用于制造这种器件结构的方法以及用于形成绝缘体上半导体衬底的方法。 半导体结构包括半导体层和设置在半导体层和衬底之间的电介质层。 电介质层包括具有第一介电常数的第一电介质区域和具有大于第一介电常数的第二介电常数的第二电介质区域。 在一个实施例中，第一电介质区域的介电常数可以小于约3.9，并且第二电介质区域的介电常数可以大于约十（10）。 绝缘体上半导体衬底包括通过高介电常数材料的绝缘体层与本体层分离的半导体层。 制造方法包括修改介电层的区域以具有较低的介电常数。
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