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    Semiconductor memory, test method of semiconductor memory and system
    1.
    发明授权
    Semiconductor memory, test method of semiconductor memory and system 失效
    半导体存储器，半导体存储器和系统的测试方法

    公开(公告)号：US07672181B2

    公开(公告)日：2010-03-02

    申请号：US12130578

    申请日：2008-05-30

    申请人： Kaoru Mori ,  Kota Hara ,  Jun Ohno

    发明人： Kaoru Mori ,  Kota Hara ,  Jun Ohno

    IPC分类号： G11C7/00

    CPC分类号： G11C29/02 ,  G11C11/401 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/4087 ,  G11C29/024 ,  G11C29/025 ,  G11C29/12015 ,  G11C2029/1202 ,  G11C2211/4061

    摘要： Each sub word line is coupled to a gate of a transfer transistor of a memory cell. A first switch of a sub word decoder couples the sub word line to a high level voltage line when a main word line is in an activation level. A second switch couples the sub word line to a low level voltage line when the main word line is in an inactivation level. A third switch couples the sub word line to the low level voltage line when a word reset signal line is in an activation level. A reset control circuit disables the inactivation of the main word line or the activation of the word reset signal line during a test mode. One of the second and third switches is forcibly turned off, and thereby, an operation failure of a sub word decoder can be detected easily.

    摘要翻译： 每个子字线耦合到存储器单元的转移晶体管的栅极。 当主字线处于激活电平时，子字解码器的第一开关将子字线耦合到高电平电压线。 当主字线处于钝化级别时，第二开关将子字线耦合到低电平电压线。 当字复位信号线处于激活电平时，第三开关将子字线耦合到低电平电压线。 复位控制电路在测试模式期间禁用主字线的失活或字复位信号线的激活。 第二和第三开关中的一个被强制关闭，从而可以容易地检测到子字解码器的操作故障。

    SEMICONDUCTOR MEMORY, TEST METHOD OF SEMICONDUCTOR MEMORY AND SYSTEM
    2.
    发明申请
    SEMICONDUCTOR MEMORY, TEST METHOD OF SEMICONDUCTOR MEMORY AND SYSTEM 失效
    半导体存储器，半导体存储器和系统的测试方法

    公开(公告)号：US20090040851A1

    公开(公告)日：2009-02-12

    申请号：US12130578

    申请日：2008-05-30

    申请人： Kaoru MORI ,  Kota Hara ,  Jun Ohno

    发明人： Kaoru MORI ,  Kota Hara ,  Jun Ohno

    IPC分类号： G11C29/00 ,  G11C7/00 ,  G11C8/00

    CPC分类号： G11C29/02 ,  G11C11/401 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/4087 ,  G11C29/024 ,  G11C29/025 ,  G11C29/12015 ,  G11C2029/1202 ,  G11C2211/4061

    摘要： Each sub word line is coupled to a gate of a transfer transistor of a memory cell. A first switch of a sub word decoder couples the sub word line to a high level voltage line when a main word line is in an activation level. A second switch couples the sub word line to a low level voltage line when the main word line is in an inactivation level. A third switch couples the sub word line to the low level voltage line when a word reset signal line is in an activation level. A reset control circuit disables the inactivation of the main word line or the activation of the word reset signal line during a test mode. One of the second and third switches is forcibly turned off, and thereby, an operation failure of a sub word decoder can be detected easily.

    摘要翻译： 每个子字线耦合到存储器单元的转移晶体管的栅极。 当主字线处于激活电平时，子字解码器的第一开关将子字线耦合到高电平电压线。 当主字线处于钝化级别时，第二开关将子字线耦合到低电平电压线。 当字复位信号线处于激活电平时，第三开关将子字线耦合到低电平电压线。 复位控制电路在测试模式期间禁用主字线的失活或字复位信号线的激活。 第二和第三开关中的一个被强制关闭，从而可以容易地检测到子字解码器的操作故障。

    SEMICONDUCTOR MEMORY, TEST METHOD OF SEMICONDUCTOR MEMORY AND SYSTEM
    3.
    发明申请
    SEMICONDUCTOR MEMORY, TEST METHOD OF SEMICONDUCTOR MEMORY AND SYSTEM 失效
    半导体存储器，半导体存储器和系统的测试方法

    公开(公告)号：US20090040850A1

    公开(公告)日：2009-02-12

    申请号：US12130480

    申请日：2008-05-30

    申请人： Kaoru Mori ,  Toshikazu Nakamura ,  Jun Ohno ,  Masaki Okuda

    发明人： Kaoru Mori ,  Toshikazu Nakamura ,  Jun Ohno ,  Masaki Okuda

    IPC分类号： G11C29/00 ,  G11C8/00

    CPC分类号： G11C8/18 ,  G11C11/401 ,  G11C11/406 ,  G11C11/40615 ,  G11C29/1201 ,  G11C29/18 ,  G11C29/48 ,  G11C2029/1802

    摘要： An address switch circuit receives a row address signal supplied to a first address terminal group and a column address signal supplied to a second address terminal group. Further, the address switch circuit receives the row address signal supplied to the second address terminal group and thereafter receives the column address signal supplied to the second address terminal group and supplies the received row address signal and the received column address signal to the row decoder and the column decoder during a second operation mode. The number of semiconductor memories that are tested at once can be increased by executing an operation test of the semiconductor memories in the second operation mode. In addition, it becomes possible to test a semiconductor memory using test assets for other semiconductor memories. Consequently, the test efficiency can be improved, and the test cost can be reduced.

    摘要翻译： 地址开关电路接收提供给第一地址端子组的行地址信号和提供给第二地址端子组的列地址信号。 此外，地址开关电路接收提供给第二地址端子组的行地址信号，然后接收提供给第二地址端子组的列地址信号，并将接收到的行地址信号和接收的列地址信号提供给行解码器， 列解码器在第二操作模式期间。 可以通过在第二操作模式下执行半导体存储器的操作测试来增加一次测试的半导体存储器的数量。 此外，可以使用用于其他半导体存储器的测试资产来测试半导体存储器。 因此，可以提高测试效率，并且可以降低测试成本。

    Semiconductor memory capable of testing a failure before programming a fuse circuit and method thereof
    4.
    发明授权
    Semiconductor memory capable of testing a failure before programming a fuse circuit and method thereof 失效
    在对熔丝电路编程之前能够测试故障的半导体存储器及其方法

    公开(公告)号：US07688659B2

    公开(公告)日：2010-03-30

    申请号：US12127161

    申请日：2008-05-27

    申请人： Kaoru Mori ,  Jun Ohno ,  Hiroyuki Kobayashi

    发明人： Kaoru Mori ,  Jun Ohno ,  Hiroyuki Kobayashi

    IPC分类号： G11C29/00

    CPC分类号： G11C29/26 ,  G11C7/1045 ,  G11C11/401 ,  G11C29/02 ,  G11C29/025 ,  G11C2029/5006 ,  G11C2029/5602

    摘要： Each program circuit outputs an operating specification signal indicating a first or second operating specification according to a program state. Each specification changing circuit is set by a corresponding block selection signal and outputs an operating specification signal indicating a second operating specification. Each timing control circuit changes an output timing of a precharge control signal for a bit line according to the operating specification signal. By the operating specification signal from the specification changing circuit, a failure can be detected in each memory block before programming a program circuit. Thereafter, the failure can be relieved by the program circuit. The output timing of the precharge control signal can be set for each memory block by a block selection signal without wiring a dedicated signal line for setting each specification changing circuit. Accordingly, increase in chip size can be minimized.

    摘要翻译： 每个程序电路根据程序状态输出指示第一或第二操作规范的操作规范信号。 每个规格改变电路由相应的块选择信号设置，并输出指示第二操作规范的操作指定信号。 每个定时控制电路根据操作指定信号改变位线的预充电控制信号的输出定时。 通过来自规范改变电路的操作规范信号，在对程序电路进行编程之前可以在每个存储器块中检测到故障。 此后，程序电路可以解除故障。 可以通过块选择信号为每个存储器块设置预充电控制信号的输出定时，而不布线用于设置每个规格改变电路的专用信号线。 因此，可以使芯片尺寸的增加最小化。

    Semiconductor device
    5.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08111575B2

    公开(公告)日：2012-02-07

    申请号：US12684652

    申请日：2010-01-08

    申请人： Kaoru Mori ,  Shinya Fujioka ,  Yoshitaka Takahashi ,  Jun Ohno ,  Akihiro Funyu ,  Shinichiro Suzuki

    发明人： Kaoru Mori ,  Shinya Fujioka ,  Yoshitaka Takahashi ,  Jun Ohno ,  Akihiro Funyu ,  Shinichiro Suzuki

    IPC分类号： G11C5/14

    CPC分类号： G11C7/04 ,  G11C11/406 ,  G11C11/40626 ,  G11C11/4072 ,  G11C11/4074

    摘要： There is provided a semiconductor device including: a temperature sensor detecting temperature; an inner circuit operating when supplied with a power supply voltage from a power supply line; a switch connected between the power supply line and the inner circuit; and a control circuit performing control in which, in a case where the temperature detected by the temperature sensor is higher than a threshold value, the switch is turned on when the inner circuit is in operation and the switch is turned off when the inner circuit is in non-operation, and in a case where the temperature detected by the temperature sensor is lower than the threshold value, the switch is turned on when the inner circuit is in operation and in non-operation.

    摘要翻译： 提供了一种半导体器件，包括：温度传感器检测温度; 当从电源线供给电源电压时工作的内部电路; 连接在电源线和内部电路之间的开关; 以及控制电路，其进行控制，其中，在由所述温度传感器检测到的温度高于阈值的情况下，当所述内部电路工作时所述开关接通，并且当所述内部电路为 在不工作的情况下，并且在由温度传感器检测到的温度低于阈值的情况下，当内部电路运行并且不工作时，开关导通。

    SEMICONDUCTOR DEVICE
    6.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20100110818A1

    公开(公告)日：2010-05-06

    申请号：US12684652

    申请日：2010-01-08

    申请人： Kaoru MORI ,  Shinya Fujioka ,  Yoshitaka Takahashi ,  Jun Ohno ,  Akihiro Funyu ,  Shinichiro Suzuki

    发明人： Kaoru MORI ,  Shinya Fujioka ,  Yoshitaka Takahashi ,  Jun Ohno ,  Akihiro Funyu ,  Shinichiro Suzuki

    IPC分类号： G11C7/00 ,  H03K17/00 ,  H03K17/56 ,  G11C8/00

    CPC分类号： G11C7/04 ,  G11C11/406 ,  G11C11/40626 ,  G11C11/4072 ,  G11C11/4074

    摘要： There is provided a semiconductor device including: a temperature sensor detecting temperature; an inner circuit operating when supplied with a power supply voltage from a power supply line; a switch connected between the power supply line and the inner circuit; and a control circuit performing control in which, in a case where the temperature detected by the temperature sensor is higher than a threshold value, the switch is turned on when the inner circuit is in operation and the switch is turned off when the inner circuit is in non-operation, and in a case where the temperature detected by the temperature sensor is lower than the threshold value, the switch is turned on when the inner circuit is in operation and in non-operation.

    摘要翻译： 提供了一种半导体器件，包括：温度传感器检测温度; 当从电源线供给电源电压时工作的内部电路; 连接在电源线和内部电路之间的开关; 以及控制电路，其进行控制，其中，在由所述温度传感器检测到的温度高于阈值的情况下，当所述内部电路工作时所述开关接通，并且当所述内部电路为 在不工作的情况下，并且在由温度传感器检测到的温度低于阈值的情况下，当内部电路运行并且不工作时，开关导通。

    Semiconductor memory, test method of semiconductor memory and system
    7.
    发明授权
    Semiconductor memory, test method of semiconductor memory and system 失效
    半导体存储器，半导体存储器和系统的测试方法

    公开(公告)号：US07675773B2

    公开(公告)日：2010-03-09

    申请号：US12130480

    申请日：2008-05-30

    申请人： Kaoru Mori ,  Toshikazu Nakamura ,  Jun Ohno ,  Masaki Okuda

    发明人： Kaoru Mori ,  Toshikazu Nakamura ,  Jun Ohno ,  Masaki Okuda

    IPC分类号： G11C11/34

    CPC分类号： G11C8/18 ,  G11C11/401 ,  G11C11/406 ,  G11C11/40615 ,  G11C29/1201 ,  G11C29/18 ,  G11C29/48 ,  G11C2029/1802

    摘要： An address switch circuit receives a row address signal supplied to a first address terminal group and a column address signal supplied to a second address terminal group. Further, the address switch circuit receives the row address signal supplied to the second address terminal group and thereafter receives the column address signal supplied to the second address terminal group and supplies the received row address signal and the received column address signal to the row decoder and the column decoder during a second operation mode. The number of semiconductor memories that are tested at once can be increased by executing an operation test of the semiconductor memories in the second operation mode. In addition, it becomes possible to test a semiconductor memory using test assets for other semiconductor memories. Consequently, the test efficiency can be improved, and the test cost can be reduced.

    摘要翻译： 地址开关电路接收提供给第一地址端子组的行地址信号和提供给第二地址端子组的列地址信号。 此外，地址开关电路接收提供给第二地址端子组的行地址信号，然后接收提供给第二地址端子组的列地址信号，并将接收到的行地址信号和接收的列地址信号提供给行解码器， 列解码器在第二操作模式期间。 可以通过在第二操作模式中执行半导体存储器的操作测试来增加一次测试的半导体存储器的数量。 此外，可以使用用于其他半导体存储器的测试资产来测试半导体存储器。 因此，可以提高测试效率，并且可以降低测试成本。

    Reduced potential generation circuit operable at low power-supply potential
    9.
    发明授权
    Reduced potential generation circuit operable at low power-supply potential 失效
    减少在低电源电位下工作的电位产生电路

    公开(公告)号：US06798276B2

    公开(公告)日：2004-09-28

    申请号：US10217408

    申请日：2002-08-14

    申请人： Katsuhiro Mori ,  Shinya Fujioka ,  Jun Ohno

    发明人： Katsuhiro Mori ,  Shinya Fujioka ,  Jun Ohno

    IPC分类号： G05F110

    CPC分类号： G05F3/262

    摘要： A power supply circuit includes a first NMOS-type current mirror circuit which compares a first potential with a second potential, a second NMOS-type current mirror circuit which compares the first potential with a third potential, and a potential setting circuit which adjusts the first potential in response to outputs of the first and second NMOS-type current mirror circuits, such that the first potential falls between the second potential and the third potential.

    摘要翻译： 电源电路包括将第一电位与第二电位进行比较的第一NMOS型电流镜电路和将第一电位与第三电位进行比较的第二NMOS型电流镜电路和调整第一电位的电位设定电路 响应于第一和第二NMOS型电流镜电路的输出的电位，使得第一电位落在第二电位和第三电位之间。

    Data transfer method and system
    10.
    发明授权
    Data transfer method and system 失效
    数据传输方式和系统

    公开(公告)号：US07730232B2

    公开(公告)日：2010-06-01

    申请号：US11113181

    申请日：2005-04-25

    申请人： Shinya Fujioka ,  Kotoku Sato ,  Hitoshi Ikeda ,  Yoshiaki Okuyama ,  Jun Ohno

    发明人： Shinya Fujioka ,  Kotoku Sato ,  Hitoshi Ikeda ,  Yoshiaki Okuyama ,  Jun Ohno

    IPC分类号： G06F13/00

    CPC分类号： G06F12/0804 ,  G06F2212/2022 ,  G11C7/1006 ,  G11C11/406 ,  G11C11/40615 ,  G11C16/06 ,  G11C16/3454

    摘要： A data transfer method and system are provided that prevent the length of a time required for writing to a flash memory from appearing on the surface as a system operation when the flash memory is used in place of an SRAM. The method of transferring data includes the steps of writing data from a controller to a volatile memory, placing the volatile memory in a transfer state, transferring the data from the volatile memory in the transfer state to a nonvolatile memory, and releasing the volatile memory from the transfer state in response to confirming completion of the transfer of the data.

    摘要翻译： 提供了一种数据传输方法和系统，其防止写入闪速存储器所需的时间长度出现在表面上，作为使用闪速存储器代替SRAM的系统操作。 传送数据的方法包括以下步骤：将数据从控制器写入易失性存储器，将易失性存储器置于传送状态，将数据从传送状态的易失性存储器传送到非易失性存储器，并将易失性存储器从 响应于确认完成数据传送的传送状态。