公开(公告)号：US08111575B2

公开(公告)日：2012-02-07

申请号：US12684652

申请日：2010-01-08

申请人： Kaoru Mori ,  Shinya Fujioka ,  Yoshitaka Takahashi ,  Jun Ohno ,  Akihiro Funyu ,  Shinichiro Suzuki

发明人： Kaoru Mori ,  Shinya Fujioka ,  Yoshitaka Takahashi ,  Jun Ohno ,  Akihiro Funyu ,  Shinichiro Suzuki

IPC分类号： G11C5/14

CPC分类号： G11C7/04 ,  G11C11/406 ,  G11C11/40626 ,  G11C11/4072 ,  G11C11/4074

摘要： There is provided a semiconductor device including: a temperature sensor detecting temperature; an inner circuit operating when supplied with a power supply voltage from a power supply line; a switch connected between the power supply line and the inner circuit; and a control circuit performing control in which, in a case where the temperature detected by the temperature sensor is higher than a threshold value, the switch is turned on when the inner circuit is in operation and the switch is turned off when the inner circuit is in non-operation, and in a case where the temperature detected by the temperature sensor is lower than the threshold value, the switch is turned on when the inner circuit is in operation and in non-operation.

摘要翻译： 提供了一种半导体器件，包括：温度传感器检测温度; 当从电源线供给电源电压时工作的内部电路; 连接在电源线和内部电路之间的开关; 以及控制电路，其进行控制，其中，在由所述温度传感器检测到的温度高于阈值的情况下，当所述内部电路工作时所述开关接通，并且当所述内部电路为 在不工作的情况下，并且在由温度传感器检测到的温度低于阈值的情况下，当内部电路运行并且不工作时，开关导通。

公开(公告)号：US20100110818A1

公开(公告)日：2010-05-06

申请号：US12684652

申请日：2010-01-08

申请人： Kaoru MORI ,  Shinya Fujioka ,  Yoshitaka Takahashi ,  Jun Ohno ,  Akihiro Funyu ,  Shinichiro Suzuki

发明人： Kaoru MORI ,  Shinya Fujioka ,  Yoshitaka Takahashi ,  Jun Ohno ,  Akihiro Funyu ,  Shinichiro Suzuki

IPC分类号： G11C7/00 ,  H03K17/00 ,  H03K17/56 ,  G11C8/00

CPC分类号： G11C7/04 ,  G11C11/406 ,  G11C11/40626 ,  G11C11/4072 ,  G11C11/4074

摘要： There is provided a semiconductor device including: a temperature sensor detecting temperature; an inner circuit operating when supplied with a power supply voltage from a power supply line; a switch connected between the power supply line and the inner circuit; and a control circuit performing control in which, in a case where the temperature detected by the temperature sensor is higher than a threshold value, the switch is turned on when the inner circuit is in operation and the switch is turned off when the inner circuit is in non-operation, and in a case where the temperature detected by the temperature sensor is lower than the threshold value, the switch is turned on when the inner circuit is in operation and in non-operation.

摘要翻译： 提供了一种半导体器件，包括：温度传感器检测温度; 当从电源线供给电源电压时工作的内部电路; 连接在电源线和内部电路之间的开关; 以及控制电路，其进行控制，其中，在由所述温度传感器检测到的温度高于阈值的情况下，当所述内部电路工作时所述开关接通，并且当所述内部电路为 在不工作的情况下，并且在由温度传感器检测到的温度低于阈值的情况下，当内部电路运行并且不工作时，开关导通。

公开(公告)号：US07114025B2

公开(公告)日：2006-09-26

申请号：US10689486

申请日：2003-10-21

申请人： Tatsuya Kanda ,  Akihiro Funyu ,  Takahiko Sato ,  Yoshiaki Okuyama ,  Jun Ohno ,  Hitoshi Ikeda

发明人： Tatsuya Kanda ,  Akihiro Funyu ,  Takahiko Sato ,  Yoshiaki Okuyama ,  Jun Ohno ,  Hitoshi Ikeda

IPC分类号： G11C7/00 ,  G06F13/00

CPC分类号： G11C11/406 ,  G11C11/401 ,  G11C11/40603 ,  G11C29/02 ,  G11C29/028 ,  G11C29/50 ,  G11C29/50016

摘要： A semiconductor memory includes a refresh timer and an arbiter for determining the order of precedence between an access operation and a refresh operation, in order to automatically perform refresh operations inside the memory. A detecting circuit operates in a test mode and outputs a detection signal indicating that the refresh operation is yet to be performed, when a new internal refresh request occurs before the refresh operation is performed. For example, the detection signal is output when the interval of access requests is short and no refresh operation can be inserted between the access operations. That is, in the semiconductor memory in which refresh operations are performed automatically, it is possible to evaluate the minimum interval of supplying access requests. As a result, the evaluation time can be reduced with a reduction in the development period of the semiconductor memory.

摘要翻译： 半导体存储器包括刷新定时器和用于确定访问操作和刷新操作之间的优先级顺序的仲裁器，以便自动执行存储器内的刷新操作。 检测电路在测试模式下工作，并且在执行刷新操作之前发生新的内部刷新请求时，输出指示刷新操作尚未执行的检测信号。 例如，当访问请求的间隔短并且在访问操作之间不能插入刷新操作时，输出检测信号。 也就是说，在自动执行刷新操作的半导体存储器中，可以评估提供访问请求的最小间隔。 结果，随着半导体存储器的显影周期的减少，可以减少评估时间。

公开(公告)号：US06842391B2

公开(公告)日：2005-01-11

申请号：US10654999

申请日：2003-09-05

申请人： Shinya Fujioka ,  Shinichi Yamada ,  Kotoku Sato ,  Jun Ohno

发明人： Shinya Fujioka ,  Shinichi Yamada ,  Kotoku Sato ,  Jun Ohno

IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4193 ,  G11C7/20

CPC分类号： G11C7/1018 ,  G11C7/22 ,  G11C2207/2227

摘要： A method for controlling a semiconductor memory in which mode register can be set in burst mode. To set an operation mode in burst mode, the semiconductor memory is changed first from the burst mode, through power-down mode, to standby mode of non-burst mode. Then the semiconductor memory is changed to mode register set mode to set the mode register when commands are input in the same predetermined sequence that is used in the non-burst mode.

摘要翻译： 一种用于控制可以以突发模式设置模式寄存器的半导体存储器的方法。 为了在突发模式下设置操作模式，首先将半导体存储器从突发模式（通过掉电模式）改变为非突发模式的待机模式。 然后，当以与非突发模式中使用的相同的预定顺序输入命令时，半导体存储器被改变为模式寄存器设置模式以设置模式寄存器。

公开(公告)号：US06798276B2

公开(公告)日：2004-09-28

申请号：US10217408

申请日：2002-08-14

申请人： Katsuhiro Mori ,  Shinya Fujioka ,  Jun Ohno

发明人： Katsuhiro Mori ,  Shinya Fujioka ,  Jun Ohno

IPC分类号： G05F110

CPC分类号： G05F3/262

摘要： A power supply circuit includes a first NMOS-type current mirror circuit which compares a first potential with a second potential, a second NMOS-type current mirror circuit which compares the first potential with a third potential, and a potential setting circuit which adjusts the first potential in response to outputs of the first and second NMOS-type current mirror circuits, such that the first potential falls between the second potential and the third potential.

摘要翻译： 电源电路包括将第一电位与第二电位进行比较的第一NMOS型电流镜电路和将第一电位与第三电位进行比较的第二NMOS型电流镜电路和调整第一电位的电位设定电路 响应于第一和第二NMOS型电流镜电路的输出的电位，使得第一电位落在第二电位和第三电位之间。

公开(公告)号：US07730232B2

公开(公告)日：2010-06-01

申请号：US11113181

申请日：2005-04-25

申请人： Shinya Fujioka ,  Kotoku Sato ,  Hitoshi Ikeda ,  Yoshiaki Okuyama ,  Jun Ohno

发明人： Shinya Fujioka ,  Kotoku Sato ,  Hitoshi Ikeda ,  Yoshiaki Okuyama ,  Jun Ohno

IPC分类号： G06F13/00

CPC分类号： G06F12/0804 ,  G06F2212/2022 ,  G11C7/1006 ,  G11C11/406 ,  G11C11/40615 ,  G11C16/06 ,  G11C16/3454

摘要： A data transfer method and system are provided that prevent the length of a time required for writing to a flash memory from appearing on the surface as a system operation when the flash memory is used in place of an SRAM. The method of transferring data includes the steps of writing data from a controller to a volatile memory, placing the volatile memory in a transfer state, transferring the data from the volatile memory in the transfer state to a nonvolatile memory, and releasing the volatile memory from the transfer state in response to confirming completion of the transfer of the data.

摘要翻译： 提供了一种数据传输方法和系统，其防止写入闪速存储器所需的时间长度出现在表面上，作为使用闪速存储器代替SRAM的系统操作。 传送数据的方法包括以下步骤：将数据从控制器写入易失性存储器，将易失性存储器置于传送状态，将数据从传送状态的易失性存储器传送到非易失性存储器，并将易失性存储器从 响应于确认完成数据传送的传送状态。

公开(公告)号：US20050094480A1

公开(公告)日：2005-05-05

申请号：US11001619

申请日：2004-12-02

申请人： Shinya Fujioka ,  Shinichi Yamada ,  Kotoku Sato ,  Jun Ohno

发明人： Shinya Fujioka ,  Shinichi Yamada ,  Kotoku Sato ,  Jun Ohno

IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4193 ,  G11C8/02

CPC分类号： G11C7/1018 ,  G11C7/22 ,  G11C2207/2227

摘要： A method for controlling a semiconductor memory in which mode register can be set in burst mode. To set an operation mode in burst mode, the semiconductor memory is changed first from the burst mode, through power-down mode, to standby mode of non-burst mode. Then the semiconductor memory is changed to mode register set mode to set the mode register when commands are input in the same predetermined sequence that is used in the non-burst mode.

摘要翻译： 一种用于控制可以以突发模式设置模式寄存器的半导体存储器的方法。 为了在突发模式下设置操作模式，首先将半导体存储器从突发模式（通过掉电模式）改变为非突发模式的待机模式。 然后，当以与非突发模式中使用的相同的预定顺序输入命令时，半导体存储器被改变为模式寄存器设置模式以设置模式寄存器。

公开(公告)号：US07057959B2

公开(公告)日：2006-06-06

申请号：US11001619

申请日：2004-12-02

申请人： Shinya Fujioka ,  Shinichi Yamada ,  Kotoku Sato ,  Jun Ohno

发明人： Shinya Fujioka ,  Shinichi Yamada ,  Kotoku Sato ,  Jun Ohno

IPC分类号： G11C7/22 ,  G11C5/14

CPC分类号： G11C7/1018 ,  G11C7/22 ,  G11C2207/2227

摘要： A method for controlling a semiconductor memory in which a mode register can be set in a burst mode. To set an operation mode in the burst mode, the semiconductor memory is changed first from the burst mode, through a power-down mode, to a standby mode of non-burst mode. Then the semiconductor memory is changed to a mode register set mode to set the mode register when commands are input in the same predetermined sequence that is used in the non-burst mode.

摘要翻译： 一种用于控制其中可以以突发模式设置模式寄存器的半导体存储器的方法。 为了在突发模式下设置操作模式，首先将半导体存储器从突发模式通过掉电模式改变为非突发模式的待机模式。 然后，当以与非突发模式中使用的相同的预定顺序输入命令时，半导体存储器被改变为模式寄存器设置模式以设置模式寄存器。

公开(公告)号：US20050185493A1

公开(公告)日：2005-08-25

申请号：US11113181

申请日：2005-04-25

申请人： Shinya Fujioka ,  Kotoku Sato ,  Hitoshi Ikeda ,  Yoshiaki Okuyama ,  Jun Ohno

发明人： Shinya Fujioka ,  Kotoku Sato ,  Hitoshi Ikeda ,  Yoshiaki Okuyama ,  Jun Ohno

IPC分类号： G06F12/00 ,  G06F12/08 ,  G06F13/16 ,  G11C7/10 ,  G11C8/00 ,  G11C11/406 ,  G11C16/12 ,  G11C16/34

CPC分类号： G06F12/0804 ,  G06F2212/2022 ,  G11C7/1006 ,  G11C11/406 ,  G11C11/40615 ,  G11C16/06 ,  G11C16/3454

摘要： A data transfer method and system are provided that prevent the length of a time required for writing to a flash memory from appearing on the surface as a system operation when the flash memory is used in place of an SRAM. The method of transferring data includes the steps of writing data from a controller to a volatile memory, placing the volatile memory in a transfer state, transferring the data from the volatile memory in the transfer state to a nonvolatile memory, and releasing the volatile memory from the transfer state in response to confirming completion of the transfer of the data.

摘要翻译： 提供了一种数据传输方法和系统，其防止写入闪速存储器所需的时间长度出现在表面上，作为使用闪速存储器代替SRAM的系统操作。 传送数据的方法包括以下步骤：将数据从控制器写入易失性存储器，将易失性存储器置于传送状态，将数据从传送状态的易失性存储器传送到非易失性存储器，并将易失性存储器从 响应于确认完成数据传送的传送状态。

公开(公告)号：US20090040850A1

公开(公告)日：2009-02-12

申请号：US12130480

申请日：2008-05-30

申请人： Kaoru Mori ,  Toshikazu Nakamura ,  Jun Ohno ,  Masaki Okuda

发明人： Kaoru Mori ,  Toshikazu Nakamura ,  Jun Ohno ,  Masaki Okuda

IPC分类号： G11C29/00 ,  G11C8/00

CPC分类号： G11C8/18 ,  G11C11/401 ,  G11C11/406 ,  G11C11/40615 ,  G11C29/1201 ,  G11C29/18 ,  G11C29/48 ,  G11C2029/1802

摘要： An address switch circuit receives a row address signal supplied to a first address terminal group and a column address signal supplied to a second address terminal group. Further, the address switch circuit receives the row address signal supplied to the second address terminal group and thereafter receives the column address signal supplied to the second address terminal group and supplies the received row address signal and the received column address signal to the row decoder and the column decoder during a second operation mode. The number of semiconductor memories that are tested at once can be increased by executing an operation test of the semiconductor memories in the second operation mode. In addition, it becomes possible to test a semiconductor memory using test assets for other semiconductor memories. Consequently, the test efficiency can be improved, and the test cost can be reduced.

摘要翻译： 地址开关电路接收提供给第一地址端子组的行地址信号和提供给第二地址端子组的列地址信号。 此外，地址开关电路接收提供给第二地址端子组的行地址信号，然后接收提供给第二地址端子组的列地址信号，并将接收到的行地址信号和接收的列地址信号提供给行解码器， 列解码器在第二操作模式期间。 可以通过在第二操作模式下执行半导体存储器的操作测试来增加一次测试的半导体存储器的数量。 此外，可以使用用于其他半导体存储器的测试资产来测试半导体存储器。 因此，可以提高测试效率，并且可以降低测试成本。