公开(公告)号：US20120229171A1

公开(公告)日：2012-09-13

申请号：US13412653

申请日：2012-03-06

申请人： Liming Xiu ,  Ming-Chieh Lin

发明人： Liming Xiu ,  Ming-Chieh Lin

IPC分类号： H03B21/00

CPC分类号： G06F1/025 ,  G06F1/02 ,  G06F1/022 ,  G06F1/0328

摘要： One of the advantages of direct frequency synthesis technique (e.g., flying-adder architecture) is its capability of generating arbitrary frequency by utilizing the time-average-frequency concept. In the clock output of the direct frequency synthesizer, instead of one type of cycle, there are two types of cycles. Unlike the conventional one-type-cycle clock wherein clock energy is concentrated at its designed frequency, Time-Average-Frequency based clock spreads some of its energy into spurious tones, which could be harmful to certain applications. The spurious tones are caused by the periodic carry sequence generated from a fractional part accumulator inside the frequency synthesizer. The invention suggests a method and an apparatus to break this periodicity and convert the spurious tones into broadband noise.

摘要翻译： 直接频率合成技术（例如飞行加法器结构）的优点之一是其通过利用时间平均频率概念产生任意频率的能力。 在直接频率合成器的时钟输出中，代替一种类型的周期，有两种类型的周期。 与其中时钟能量集中在其设计频率的常规单周期时钟不同，基于时间 - 平均频率的时钟将其一些能量扩展到伪噪声，这可能对某些应用有害。 伪噪声是由频率合成器内的分数分量累加器产生的周期性进位序列引起的。 本发明提出了一种破坏这种周期性并将伪噪声转换成宽带噪声的方法和装置。

公开(公告)号：US09128536B2

公开(公告)日：2015-09-08

申请号：US13412653

申请日：2012-03-06

申请人： Liming Xiu ,  Ming-Chieh Lin

发明人： Liming Xiu ,  Ming-Chieh Lin

IPC分类号： G06F1/02 ,  G06F1/03 ,  G06F1/025

CPC分类号： G06F1/025 ,  G06F1/02 ,  G06F1/022 ,  G06F1/0328

摘要： One of the advantages of direct frequency synthesis technique (e.g., flying-adder architecture) is its capability of generating arbitrary frequency by utilizing the time-average-frequency concept. In the clock output of the direct frequency synthesizer, instead of one type of cycle, there are two types of cycles. Unlike the conventional one-type-cycle clock wherein clock energy is concentrated at its designed frequency, Time-Average-Frequency based clock spreads some of its energy into spurious tones, which could be harmful to certain applications. The spurious tones are caused by the periodic carry sequence generated from a fractional part accumulator inside the frequency synthesizer. The invention suggests a method and an apparatus to break this periodicity and convert the spurious tones into broadband noise.

摘要翻译： 直接频率合成技术（例如飞行加法器结构）的优点之一是其通过利用时间平均频率概念产生任意频率的能力。 在直接频率合成器的时钟输出中，代替一种类型的周期，有两种类型的周期。 与其中时钟能量集中在其设计频率的常规单周期时钟不同，基于时间 - 平均频率的时钟将其一些能量扩展到伪噪声，这可能对某些应用有害。 伪噪声是由频率合成器内的分数分量累加器产生的周期性进位序列引起的。 本发明提出了一种破坏这种周期性并将伪噪声转换成宽带噪声的方法和装置。

公开(公告)号：US08890591B1

公开(公告)日：2014-11-18

申请号：US14140016

申请日：2013-12-24

申请人： Liming Xiu

发明人： Liming Xiu

IPC分类号： H03L7/06

CPC分类号： H03L1/022 ,  H03L1/027 ,  H03L7/099 ,  H03L7/0995 ,  H03L7/18

摘要： A Time-Average-Frequency direct period synthesizer is used to improve crystal-less frequency generator's frequency stability. It includes (a) a temperature sensor circuit to compensate temperature-induced frequency instability; (b) a voltage sensor circuit to compensate voltage-induced frequency instability; (c) a calibration circuit to correct manufacture-related frequency error; (d) a frequency control word update circuit to receive the temperature- and voltage-related frequency adjustments, and the calibration-related adjustment, to generate the corresponding frequency control word in a predetermined schedule; (f) a Time-Average-Frequency direct period synthesizer to receive said frequency control word in the predetermined schedule and produce a clock signal with a frequency that is stable and accurate by counteracting the frequency variation caused by crystal-less oscillators' temperature and voltage dependence and correcting the frequency error introduced in manufacture process. Methods of correcting crystal-less oscillators' frequency error and compensating its frequency variation are also disclosed.

摘要翻译： 时频平均频率直接周期合成器用于提高无晶体频率发生器的频率稳定性。 它包括（a）温度传感器电路，用于补偿温度引起的频率不稳定性; （b）用于补偿电压引起的频率不稳定性的电压传感器电路; （c）校正制造相关频率误差的校准电路; （d）频率控制字更新电路，用于接收温度和电压相关的频率调节和校准相关的调整，以在预定时间表中产生相应的频率控制字; （f）时间平均频率直接周期合成器，用于在预定时间表中接收所述频率控制字，并通过抵消由无晶体振荡器的温度和电压引起的频率变化，产生具有稳定和准确的频率的时钟信号 依赖和纠正制造过程中引入的频率误差。 还公开了无结晶振荡器的频率误差的校正方法和补偿其频率变化。

公开(公告)号：US08258834B2

公开(公告)日：2012-09-04

申请号：US12889524

申请日：2010-09-24

申请人： Liming Xiu

发明人： Liming Xiu

IPC分类号： H03L7/06

CPC分类号： H03L7/095

摘要： A lock detector for a phase lock loop (PLL) includes: first and second pulse width extenders, performing pulse width extension on first and second pulses for generating third and fourth pulses, respectively; first and second delay circuits, delaying the third and the fourth pulses into first and second sampling clocks, respectively; and a cross-sampling circuit, sampling the third pulse based on the second sampling clock and sampling the fourth pulse based on the first sampling clock to indicate whether the PLL is locked.

摘要翻译： 用于锁相环（PLL）的锁定检测器包括：第一和第二脉冲宽度扩展器，分别在用于产生第三和第四脉冲的第一和第二脉冲上执行脉冲宽度扩展; 第一和第二延迟电路，分别将第三和第四脉冲延迟到第一和第二采样时钟; 和交叉采样电路，基于第二采样时钟对第三脉冲进行采样，并且基于第一采样时钟对第四脉冲进行采样，以指示PLL是否被锁定。

公开(公告)号：US08195972B2

公开(公告)日：2012-06-05

申请号：US12628339

申请日：2009-12-01

申请人： Karl Renner ,  Walter Heinrich Demmer ,  Liming Xiu

发明人： Karl Renner ,  Walter Heinrich Demmer ,  Liming Xiu

IPC分类号： G06F1/00 ,  G06F1/04 ,  G06F11/00 ,  H03L7/06

CPC分类号： G06F1/08 ,  H03L7/18

摘要： Synchronous circuitry for processing digital data in which the data are filtered to compensate for expected jitter in time-average frequency clock signals. Time-average frequency synthesis circuitry generates internal clock signals of a desired frequency, for example as based on a recovered clock signal from an input data stream, in a manner in which not all periods of the clock signal are of uniform duration. A jitter precorrection filter is inserted into the data path to apply a variable delay to pre-correct for distortion caused by jitter in the clock cycle. In embodiments of the invention using a flying-adder architecture to generate the clock signal, coefficients of the digital filer realizing the jitter precorrection filter are calculated according to the currently-selected oscillator phase and according to a fractional portion of a digital frequency control word.

摘要翻译： 用于处理数字数据的同步电路，其中数据被滤波以补偿时间平均频率时钟信号中的预期抖动。 时间平均频率合成电路以不是所有的时钟信号周期具有均匀持续时间的方式，例如基于来自输入数据流的恢复的时钟信号来产生期望频率的内部时钟信号。 抖动预校正滤波器被插入到数据路径中以应用可变延迟来预校正由时钟周期中的抖动引起的失真。 在使用飞加法器架构来生成时钟信号的本发明的实施例中，根据当前选择的振荡器相位并根据数字频率控制字的小数部分来计算实现抖动预校正滤波器的数字滤波器的系数。

公开(公告)号：US08120389B2

公开(公告)日：2012-02-21

申请号：US12536181

申请日：2009-08-05

申请人： Liming Xiu

发明人： Liming Xiu

IPC分类号： H03B21/00 ,  H03L7/06

CPC分类号： H03L7/16 ,  G06F1/025 ,  G06F1/04

摘要： To make Flying-Adder architecture even more powerful, a new concept, time-average-frequency, is incorporated into the clock generation circuitry. This is a fundamental breakthrough since it attacks the clock generation problem from its root: how is the clock signal used in real systems? By investigating from this direction, a much more powerful architecture, fixed-VCO-Flying-Adder architecture, is created. Furthermore, based on fixed-VCO-Flying-Adder frequency synthesizer and time-average-frequency, a new type of component called Digital-to-Frequency Converter (DFC) is born.

摘要翻译： 为了使飞加法架构更加强大，将时间平均频率的新概念并入时钟生成电路。 这是一个根本的突破，因为它从根本上攻击时钟生成问题：实时系统中使用的时钟信号如何？ 通过从这个方向调查，创建了一个更强大的架构，固定VCO-Flying-Adder架​​构。 此外，基于固定VCO-Flying-Adder频率合成器和时间平均频率，诞生了一种称为数字 - 频率转换器（DFC）的新型组件。

公开(公告)号：US07702708B2

公开(公告)日：2010-04-20

申请号：US11221674

申请日：2005-09-07

申请人： Gonggui Xu ,  Haydar Bilhan ,  Liming Xiu

发明人： Gonggui Xu ,  Haydar Bilhan ,  Liming Xiu

IPC分类号： G06F1/02 ,  H03B19/00

CPC分类号： G06F1/025

摘要： An apparatus employing control words to present a synthesized output signal having an output frequency and a delay with respect to an input signal includes: (a) A multiplexer receiving the input signal and having an output and an address input. (b) An output unit generates the output signal in response to a drive signal from the multiplexer. (c) A first register coupled with the multiplexer output. (d) A second register coupled with the multiplexer and the first register. The first register responds to a multiplexer output signal to provide a first control signal to the second register based upon the control words. The second register responds to the multiplexer output signal to provide a second control signal to the address input based upon the first control signal and the control words. The multiplexer presents the drive signal in response to the second control signal.

摘要翻译： 一种采用控制字呈现具有输出频率和相对于输入信号的延迟的合成输出信号的装置包括：（a）多路复用器，接收输入信号并具有输出和地址输入。 （b）输出单元响应于来自多路复用器的驱动信号产生输出信号。 （c）与多路复用器输出耦合的第一寄存器。 （d）与复用器和第一寄存器耦合的第二寄存器。 第一寄存器响应多路复用器输出信号，以基于控制字向第二寄存器提供第一控制信号。 第二寄存器响应多路复用器输出信号，以基于第一控制信号和控制字向地址输入提供第二控制信号。 复用器响应于第二控制信号呈现驱动信号。

公开(公告)号：US20090103604A1

公开(公告)日：2009-04-23

申请号：US12254381

申请日：2008-10-20

申请人： Liming Xiu ,  Grady Cook ,  Daniel Dudek ,  Hongbing Lian ,  Yihe Hu ,  Christopher S. Tracy

发明人： Liming Xiu ,  Grady Cook ,  Daniel Dudek ,  Hongbing Lian ,  Yihe Hu ,  Christopher S. Tracy

IPC分类号： H04N7/12

CPC分类号： H04N21/4305 ,  H03L7/0996 ,  H03L7/18 ,  H04N21/42615 ,  H04N21/434

摘要： This invention uses a flying adder frequency synthesis circuit to provide the required frequency adjustments to accommodate the varying encoding density of a MPEG2 video data stream. This invention adjusts the local clock based on the information extracted from the program clock reference signal in the incoming data. This invention replaces an external or internal voltage-controlled crystal oscillator using a phase locked loop circuit on the video processing integrated circuit.

摘要翻译： 本发明使用飞行加法器频率合成电路来提供所需的频率调整以适应MPEG2视频数据流的变化的编码密度。 本发明基于从输入数据中的节目时钟参考信号中提取的信息来调整本地时钟。 本发明使用视频处理集成电路上的锁相环电路代替外部或内部压控晶体振荡器。

公开(公告)号：US09740235B1

公开(公告)日：2017-08-22

申请号：US14639332

申请日：2015-03-05

申请人： Liming Xiu

发明人： Liming Xiu

IPC分类号： G06F1/08 ,  G06F1/12

CPC分类号： G06F1/08 ,  G06F1/10 ,  G06F1/12

摘要： An interface adapter for facilitating the data communication among computation modules in a Network-on-Chip SoC comprises 1) a FIFO block having certain number of storage cells for temporarily storing the data to be transported between two communicating modules; 2) a TAF-DPS clock generator and a multi-phase generator attached at the FIFO write side for generating the write clock for FIFO and the driving clock for the transmitter, a TAF-DPS clock generator and a multi-phase generator attached at the FIFO read side for generating the read clock for FIFO and the driving clock for the receiver; 3) a write pointer controller and a read pointer controller for reading the FIFO status and controlling the TAF-DPS clock generators at the write side and at the read side, respectively. A design scheme of using said interface adapters in Network-on-Chip SoC design includes a plurality of computation modules, routing modules, said interface adapters, a network of communication link, a network of global clock distribution. Methods of creating the interface adapter and using it in the Network-on-Chip SoC design are also disclosed.

公开(公告)号：US09621173B1

公开(公告)日：2017-04-11

申请号：US14945468

申请日：2015-11-19

申请人： Liming Xiu

发明人： Liming Xiu

IPC分类号： G06F17/50 ,  H03L7/197 ,  H03K19/173 ,  H03K19/017 ,  H03K19/018 ,  G06F1/10 ,  G06F1/12 ,  H03L7/099 ,  H03K19/0185 ,  H03K19/096

CPC分类号： H03L7/197 ,  G06F1/10 ,  G06F1/12 ,  G06F17/5045 ,  G06F17/505 ,  G06F17/5054 ,  H03K19/01728 ,  H03K19/01855 ,  H03K19/096 ,  H03K19/1737 ,  H03L7/0812 ,  H03L7/0991 ,  H03L7/16 ,  H03L7/18

摘要： Circuits of a TAF-DPS clock generator implemented on programmable logic chip comprise: 1) a base time unit generator created from configurable blocks, or on-chip PLL, or on-chip DLL, said base time unit generator produces a plurality of phase-evenly-spaced-signals; 2) a TAF-DPS frequency synthesizer created by configuring configurable blocks of said programmable logic chip, said TAF-DPS frequency synthesizer takes said plurality of phase-evenly-spaced-signals as its input. Methods of creating flexible clock signal to drive application comprise: 1) selecting one or more strategic areas in said programmable logic chip; 2) creating one or more TAF-DPS clock generator for each said area by using the configurable resource in said area; 3) creating control function to control the frequency and duty-cycle of the TAF-DPS clock generator output, said control function can be circuit created from configuring configurable blocks, said control function can also be achieved by software; 4) driving the circuits in application by the flexible clock generated from said TAF-DPS clock generator.