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公开(公告)号：US20240324223A1
公开(公告)日：2024-09-26
申请号：US18731940
申请日：2024-06-03
Applicant: Lodestar Licensing Group LLC
Inventor： S. M. Istiaque Hossain , Prakash Rau Mokhna Rau , Arun Kumar Dhayalan , Damir Fazil , Joel D. Peterson , Anilkumar Chandolu , Albert Fayrushin , George Matamis , Christopher Larsen , Rokibul Islam
IPC: H10B43/27 , G11C5/02 , G11C5/06 , G11C16/04 , H01L21/768
CPC classification number: H10B43/27 , G11C5/025 , G11C5/06 , G11C16/0466 , H01L21/76802 , H01L21/76877
Abstract: Some embodiments include an integrated assembly having a first deck. The first deck has first memory cell levels alternating with first insulative levels. A second deck is over the first deck. The second deck has second memory cell levels alternating with second insulative levels. A cell-material-pillar passes through the first and second decks. Memory cells are along the first and second memory cell levels and include regions of the cell-material-pillar. An intermediate level is between the first and second decks. The intermediate level includes a buffer region adjacent the cell-material-pillar. The buffer region includes a composition different from the first and second insulative materials, and different from the first and second conductive regions. Some embodiments include methods of forming integrated assemblies.
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2.发明申请公开(公告)号：US20250071996A1
公开(公告)日：2025-02-27
申请号：US18944590
申请日：2024-11-12
Applicant: Lodestar Licensing Group, LLC
Inventor： Darwin A. Clampitt , Shawn D. Lyonsmith , Matthew J. King , Lisa M. Clampitt , John Hopkins , Kevin Y. Titus , Indra V. Chary , Martin Jared Barclay , Anilkumar Chandolu , Pavithra Natarajan , Roger W. Lindsay
IPC: H10B43/27 , G11C16/04 , H01L21/02 , H01L21/67 , H01L23/522 , H01L23/528 , H10B43/10 , H10B51/20
Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a first deck located over a substrate, and a second deck located over the first deck, and pillars extending through the first and second decks. The first deck includes first memory cells, first control gates associated with the first memory cells, and first conductive paths coupled to the first control gates. The second conductive paths include second conductive pads located on a first level of the apparatus over the substrate. The second deck includes second memory cells, second control gates associated with the second memory cells, and second conductive paths coupled to the second control gates. The second conductive paths include second conductive pads located on a second level of the apparatus. The first and second conductive pads having lengths in a direction perpendicular to a direction from the first deck to the second deck.
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3.发明授权公开(公告)号：US12167599B2
公开(公告)日：2024-12-10
申请号：US18083991
申请日：2022-12-19
Applicant: Lodestar Licensing Group, LLC
Inventor： Darwin A. Clampitt , Shawn D. Lyonsmith , Matthew J. King , Lisa M. Clampitt , John Hopkins , Kevin Y. Titus , Indra V. Chary , Martin Jared Barclay , Anilkumar Chandolu , Pavithra Natarajan , Roger W. Lindsay
IPC: H10B43/27 , G11C16/04 , H01L21/02 , H01L21/67 , H01L23/522 , H01L23/528 , H10B43/10 , H10B51/20
Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a first deck located over a substrate, and a second deck located over the first deck, and pillars extending through the first and second decks. The first deck includes first memory cells, first control gates associated with the first memory cells, and first conductive paths coupled to the first control gates. The second conductive paths include second conductive pads located on a first level of the apparatus over the substrate. The second deck includes second memory cells, second control gates associated with the second memory cells, and second conductive paths coupled to the second control gates. The second conductive paths include second conductive pads located on a second level of the apparatus. The first and second conductive pads having lengths in a direction perpendicular to a direction from the first deck to the second deck.
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Patent Agency Ranking
公开(公告)号：US20240334703A1
公开(公告)日：2024-10-03
申请号：US18738970
申请日：2024-06-10
Applicant: Lodestar Licensing Group LLC
Inventor： Anilkumar Chandolu , Indra V. Chary
Abstract: Microelectronic devices include a stack structure with a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. Conductive contact structures extend through the stack structure. An insulative material is between the conductive contact structures and the tiers of the stack structure. In a lower tier portion of the stack structure, a conductive structure, of the conductive structures, has a portion extending a first width between a pair of the conductive contact structures. In a portion of the stack structure above the lower tier portion, an additional conductive structure, of the conductive structures, has an additional portion extending a second width between the pair of the conductive contact structures. The second width is greater than the first width. Related methods and electronic systems are also disclosed.
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公开(公告)号：US11984364B2
公开(公告)日：2024-05-14
申请号：US17207989
申请日：2021-03-22
Applicant: Lodestar Licensing Group LLC
Inventor： Anilkumar Chandolu , Lisa R. Copenspire-Ross , Michael D. Kenney
Abstract: Semiconductor devices having measurement features and associated systems and methods are disclosed herein. In one embodiment, a semiconductor device includes a plurality of stacked semiconductor dies each having measurement features formed along an outer periphery of a surface thereof. One or more image capture devices can image the semiconductor device and a controller can detect the measurement features in imaging data received from the image capture devices. The controller can further determine the distance between two or more of the measurement features to estimate a bond line thickness between semiconductor dies in the stack.
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公开(公告)号：US20240371706A1
公开(公告)日：2024-11-07
申请号：US18661326
申请日：2024-05-10
Applicant: Lodestar Licensing Group LLC
Inventor： Anilkumar Chandolu , Lisa R. Copenspire-Ross , Michael D. Kenney
Abstract: Semiconductor devices having measurement features and associated systems and methods are disclosed herein. In one embodiment, a semiconductor device includes a plurality of stacked semiconductor dies each having measurement features formed along an outer periphery of a surface thereof. One or more image capture devices can image the semiconductor device and a controller can detect the measurement features in imaging data received from the image capture devices. The controller can further determine the distance between two or more of the measurement features to estimate a bond line thickness between semiconductor dies in the stack.
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7.发明公开公开(公告)号：US20240357820A1
公开(公告)日：2024-10-24
申请号：US18762200
申请日：2024-07-02
Applicant: Lodestar Licensing Group LLC
Inventor： S M Istiaque Hossain , Tom J. John , Darwin A. Clampitt , Anilkumar Chandolu , Parkash Rau Mokhna Rau , Christopher J. Larsen , Kye Hyun Baek
IPC: H10B43/27 , H01L21/768
CPC classification number: H10B43/27 , H01L21/76802 , H01L21/76877 , H01L21/76897
Abstract: An electronic device comprising lower and upper decks adjacent to a source. The lower and upper decks comprise tiers of alternating conductive materials and dielectric materials. Memory pillars in the lower and upper decks are configured to be operably coupled to the source. The memory pillars comprise contact plugs in the upper deck, cell films in the lower and upper decks, and fill materials in the lower and upper decks. The cell films in the upper deck are adjacent to the contact plugs and the fill materials in the upper deck are adjacent to the contact plugs. Dummy pillars are in a central region of the lower deck and the upper deck. The dummy pillars comprise an oxide material in the upper deck, the oxide material contacting the contact plugs and the fill materials. Additional electronic devices and related systems and methods are also disclosed.
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公开(公告)号：US12004351B2
公开(公告)日：2024-06-04
申请号：US17869732
申请日：2022-07-20
Applicant: Lodestar Licensing Group LLC
Inventor： S. M. Istiaque Hossain , Prakash Rau Mokhna Rau , Arun Kumar Dhayalan , Damir Fazil , Joel D. Peterson , Anilkumar Chandolu , Albert Fayrushin , George Matamis , Christopher Larsen , Rokibul Islam
IPC: H10B43/27 , G11C5/02 , G11C5/06 , G11C16/04 , H01L21/768
CPC classification number: H10B43/27 , G11C5/025 , G11C5/06 , G11C16/0466 , H01L21/76802 , H01L21/76877
Abstract: Some embodiments include an integrated assembly having a first deck. The first deck has first memory cell levels alternating with first insulative levels. A second deck is over the first deck. The second deck has second memory cell levels alternating with second insulative levels. A cell-material-pillar passes through the first and second decks. Memory cells are along the first and second memory cell levels and include regions of the cell-material-pillar. An intermediate level is between the first and second decks. The intermediate level includes a buffer region adjacent the cell-material-pillar. The buffer region includes a composition different from the first and second insulative materials, and different from the first and second conductive regions. Some embodiments include methods of forming integrated assemblies.
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