公开(公告)号：US10658046B2

公开(公告)日：2020-05-19

申请号：US15841622

申请日：2017-12-14

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Kuen-Long Chang ,  Ken-Hui Chen ,  Su-Chueh Lo ,  Chun-Yu Liao

IPC: G11C7/10 ,  G11C16/26 ,  G11C16/04 ,  G11C7/06 ,  G06F12/02 ,  G11C11/4093 ,  G06F13/40 ,  G11C16/20

Abstract: The embodiment of the present invention discloses a memory device and a method for operating the same. The memory device includes a memory array and a logic circuit. The logic circuit is coupled to the memory array, and is configured to perform a corresponding operation in response to an operation command from a controller. When an interruption event occurs during the corresponding operation, the logic circuit records a memory status, and the logic circuit further is configured to output the memory status to the controller in response to a status read command from the controller.

公开(公告)号：US10475510B2

公开(公告)日：2019-11-12

申请号：US15850280

申请日：2017-12-21

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shang-Chi Yang ,  Chun-Yu Liao ,  Ken-Hui Chen

IPC: G11C13/00 ,  G11C11/16 ,  G11C27/02

Abstract: A memory device including an array of memory cells including bit lines, and biasing circuitry cells. A sense amplifier has a data line input connected to a data line, and a reference input. The controllable reference current source can be connected to the reference input of the sense amplifier. Control circuits on the device are configured to cause execution of a read operation, where the read operation includes a first phase in which the array is biased to induce leakage current on the selected bit line, and a second phase in which the array is biased to read a selected memory cell on the selected bit line. A circuit on the device is configured to sample the leakage current in the first phase, and to control the controllable reference current source during the second phase, as a function of the sampled leakage current.

公开(公告)号：US20170351636A1

公开(公告)日：2017-12-07

申请号：US15411731

申请日：2017-01-20

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Ken-Hui Chen ,  Kuen-Long Chang ,  Su-Chueh Lo ,  Chun-Yu Liao

IPC: G06F13/42 ,  G06F13/16

CPC classification number: G06F13/4234 ,  G06F13/1631 ,  G06F13/1673 ,  G06F13/4291

Abstract: A memory device includes command logic allowing for a command protocol allowing interruption of a first command sequence, such as a page write sequence, and then to proceed directly to receive and decode a second command sequence, such as a read sequence, without latency associated, completing the first command sequence. Also, the command logic is configured to be responsive to a third command sequence after the second command sequence and its associated embedded operation have been completed, which completes the interrupted first command sequence and enables execution of an embedded operation identified by the first command sequence. A memory controller supporting such protocols is described.

公开(公告)号：US10657051B2

公开(公告)日：2020-05-19

申请号：US15841640

申请日：2017-12-14

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Su-Chueh Lo ,  Chun-Yu Liao

IPC: G11C16/26 ,  G06F12/06 ,  G11C11/417 ,  G11C11/16 ,  G11C7/20 ,  G11C7/10 ,  G11C11/413 ,  G11C29/50 ,  G06F3/06

Abstract: Provided is a memory device including: a memory array, including a flag memory array having a plurality of flag memory cells and a data memory array having a plurality of data memory cells, the corresponding flag memory cells being used to record whether the corresponding data memory cells have been written or not. In initialization, the flag memory array is initialized by the control circuit but the data memory array is not initialized.

公开(公告)号：US10475492B1

公开(公告)日：2019-11-12

申请号：US16047550

申请日：2018-07-27

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shang-Chi Yang ,  Chun-Yu Liao ,  Yi-Wei Chang

IPC: G11C7/22 ,  G11C7/10 ,  G11C7/06

Abstract: A memory device comprises an array of memory cells, and a plurality of sense amplifiers coupled with the memory cells. A controller is configured to execute a read operation in response to a command and address, including a read cycle in which the memory cells at the address are electrically coupled to the sense amplifiers, and in which the memory cells at the address are electrically decoupled from the sense amplifiers in response to a timing signal.

公开(公告)号：US10289596B2

公开(公告)日：2019-05-14

申请号：US15411731

申请日：2017-01-20

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Ken-Hui Chen ,  Kuen-Long Chang ,  Su-Chueh Lo ,  Chun-Yu Liao

IPC: G06F13/42 ,  G06F13/16

Abstract: A memory device includes command logic allowing for a command protocol allowing interruption of a first command sequence, such as a page write sequence, and then to proceed directly to receive and decode a second command sequence, such as a read sequence, without latency associated, completing the first command sequence. Also, the command logic is configured to be responsive to a third command sequence after the second command sequence and its associated embedded operation have been completed, which completes the interrupted first command sequence and enables execution of an embedded operation identified by the first command sequence. A memory controller supporting such protocols is described.

公开(公告)号：US10115441B1

公开(公告)日：2018-10-30

申请号：US15654752

申请日：2017-07-20

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shang-Chi Yang ,  Chun-Yu Liao

IPC: G11C8/00 ,  G11C8/10 ,  G11C8/12 ,  G06F11/10 ,  G11C8/08 ,  G11C16/34 ,  G11C17/18

Abstract: A row decoder includes a plurality of address lines, a first selection circuit and a second selection circuit. The first selection circuit is coupled to the address lines and with a latch function, and configured to enable and latch a first selection signal to select a first word line in a first cell array. The second selection circuit is coupled to the address lines and without the latch function, and configured to enable a second selection signal to select a second word line in a second cell array.