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公开(公告)号：US20200295772A1
公开(公告)日：2020-09-17
申请号：US16809581
申请日：2020-03-05
Applicant: MEDIATEK INC.
Inventor： Wei-Hsiang Huang , Yun-Shiang Shu , Su-Hao Wu
Abstract: A signal processing system includes an analog-to-digital converter (ADC) that is used to convert a first analog value into a first digital value and convert a second analog value into a second digital value. The ADC includes a first digital-to-analog converter (DAC) circuit and a second DAC circuit operating in different voltage domains. A first bit segment and a second bit segment of each digital value are determined via the first DAC circuit and the second DAC circuit, respectively. An analog injection value is injected to the second analog value, the analog injection value is converted from a digital injection value formed by a subset of bits of the second bit segment of the first digital value, and the second bit segment of the second digital value is derived from injecting the digital injection value to a digital value determined by the second DAC circuit.
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公开(公告)号：US08988265B2
公开(公告)日：2015-03-24
申请号：US13941598
申请日：2013-07-15
Applicant: MediaTek Inc.
Inventor： Yun-Shiang Shu
Abstract: A comparison circuit is provided and includes first and second comparators and a first time-to-digital comparator. The first comparator with a first offset voltage receives an input signal and generates a first comparison signal and a first inverse comparison signal. The second comparator receives the input signal and generates a second comparison signal and a second inverse comparison signal. The first offset voltage is larger than the second offset voltage. The first time-to-digital comparator receives the first comparison signal and the second inverse comparison signal and generates first and second determination signals according to the first comparison signal and the second inverse comparison signal. The first and second determination signals indicate whether a voltage of the input signal is larger than a first middle voltage. The first middle voltage is equal to a half of the sum of the first offset voltage and the second offset voltage.
Abstract translation: 提供比较电路并包括第一和第二比较器和第一时间 - 数字比较器。 具有第一偏移电压的第一比较器接收输入信号并产生第一比较信号和第一反比较信号。 第二比较器接收输入信号并产生第二比较信号和第二反比较信号。 第一偏移电压大于第二偏移电压。 第一时间数字比较器接收第一比较信号和第二反比较信号，并根据第一比较信号和第二反比较信号产生第一和第二确定信号。 第一和第二确定信号指示输入信号的电压是否大于第一中间电压。 第一中间电压等于第一偏移电压和第二偏移电压之和的一半。
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公开(公告)号：US11265010B2
公开(公告)日：2022-03-01
申请号：US16837417
申请日：2020-04-01
Applicant: MEDIATEK INC.
Inventor： Yun-Shiang Shu , Su-Hao Wu , Hung-Yi Hsieh , Albert Yen-Chih Chiou
IPC: H03M3/00
Abstract: An incremental analog-to-digital converter (ADC) with high accuracy. The incremental ADC has a delta-sigma modulator, performing delta-sigma modulation on an analog input signal to output a quantized signal, and a digital filter, receiving the quantized signal to generate a digital representation of the analog input signal. A loop filter of the delta-sigma modulator has a preset circuit. In the preset circuit, the output terminal of the loop filter is preset rather than being reset during the reset phase of the incremental ADC.
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4.发明授权公开(公告)号：US09831885B2
公开(公告)日：2017-11-28
申请号：US15497240
申请日：2017-04-26
Applicant: MEDIATEK Inc.
Inventor： Yun-Shiang Shu
CPC classification number: H03M1/066 , H03M1/001 , H03M1/0673 , H03M1/145 , H03M1/68 , H03M3/338 , H03M3/344
Abstract: The invention provides a system for conversion between analog domain and digital domain with mismatch error shaping, including a DAC, a first injection circuit coupled to the DAC, and a second injection circuit coupled to the DAC. The DAC generates a first analog value in response to a first digital value, and generates a second analog value in response to a second digital value. The first injection circuit enables an analog injection value to be injected to the second analog value when the DAC generates the second analog value, wherein the analog injection value is converted from a digital injection value formed by a subset of bits of the first digital value. The second injection circuit injects the digital injection value to the second digital value, or combines the digital injection value and a related value obtained according to the second analog value.
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5.发明授权Method and apparatus for performing offset adjustment upon dynamic comparator 有权用于在动态比较器上执行偏移调整的方法和装置公开(公告)号：US09077320B2
公开(公告)日：2015-07-07
申请号：US14028557
申请日：2013-09-17
Applicant: MEDIATEK INC.
Inventor： Yun-Shiang Shu
CPC classification number: H03K5/003 , H03K5/2481 , H03M1/361
Abstract: An offset adjustment circuit of a dynamic comparator has a detection unit and a control unit. The detection unit detects whether a comparator offset possessed by the dynamic comparator is deviated from a target offset setting, and accordingly generates a detection result. The control unit adjusts a voltage setting of at least one input received by the dynamic comparator when the detection result indicates that the comparator offset is deviated from the target offset setting.
Abstract translation: 动态比较器的偏移调整电路具有检测单元和控制单元。 检测单元检测动态比较器拥有的比较器偏移是否偏离目标偏移设置，并且因此产生检测结果。 当检测结果指示比较器偏移偏离目标偏移设置时，控制单元调整由动态比较器接收的至少一个输入的电压设置。
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Patent Agency Ranking
6.发明申请METHOD AND APPARATUS FOR PERFORMING OFFSET ADJUSTMENT UPON DYNAMIC COMPARATOR 有权用于在动态比较器上执行偏移调整的方法和装置公开(公告)号：US20140077860A1
公开(公告)日：2014-03-20
申请号：US14028557
申请日：2013-09-17
Applicant: MEDIATEK INC.
Inventor： Yun-Shiang Shu
IPC: H03K5/003
CPC classification number: H03K5/003 , H03K5/2481 , H03M1/361
Abstract: An offset adjustment circuit of a dynamic comparator has a detection unit and a control unit. The detection unit detects whether a comparator offset possessed by the dynamic comparator is deviated from a target offset setting, and accordingly generates a detection result. The control unit adjusts a voltage setting of at least one input received by the dynamic comparator when the detection result indicates that the comparator offset is deviated from the target offset setting.
Abstract translation: 动态比较器的偏移调整电路具有检测单元和控制单元。 检测单元检测动态比较器拥有的比较器偏移是否偏离目标偏移设置，并且因此产生检测结果。 当检测结果指示比较器偏移偏离目标偏移设置时，控制单元调整由动态比较器接收的至少一个输入的电压设置。
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公开(公告)号：US20140070969A1
公开(公告)日：2014-03-13
申请号：US14016246
申请日：2013-09-03
Applicant: MEDIATEK INC.
Inventor： Yun-Shiang Shu
IPC: H03M3/00
Abstract: A delta-sigma analog-to-digital converter (ΔΣ ADC) has a delta-sigma modulator, a decimation filter and an error suppression circuit. The delta-sigma modulator receives an analog input, and converts the analog input into a first digital output. The decimation filter is coupled to the delta-sigma modulator, and generates a second digital output according to the first digital output. The error suppression circuit is coupled to the decimation filter, and receives an error input and injects an error output into the second digital output according to the error input.
Abstract translation: Δ-Σ模数转换器（DeltaSigma ADC）具有Δ-Σ调制器，抽取滤波器和误差抑制电路。 Δ-Σ调制器接收模拟输入，并将模拟输入转换为第一数字输出。 抽取滤波器耦合到Δ-Σ调制器，并根据第一数字输出产生第二数字输出。 误差抑制电路耦合到抽取滤波器，并接收错误输入，并根据误差输入将错误输出注入第二数字输出。
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公开(公告)号：US10205466B2
公开(公告)日：2019-02-12
申请号：US15830000
申请日：2017-12-04
Applicant: MEDIATEK INC.
Inventor： Qiang Zhou , Hua Wang , Yun-Shiang Shu , Bao-Chi Peng
Abstract: An electronic device has a transmit circuit and a processing circuit. The processing circuit outputs a first portion of compressive sensing (CS) samples corresponding to a signal segment to another electronic device via the transmit circuit, and selectively outputs a second portion of the CS samples corresponding to the signal segment to another electronic device via the transmit circuit according to a response of another electronic device. In this way, a balance between the compression ratio and the reconstruction quality/speed can be achieved. Moreover, the signal reconstruction performed at the processing circuit may employ a multi-resolution/multi-scale reconstruction scheme to achieve a balance between the dictionary size and the reconstruction quality/speed, and/or may employ a multi-stage reconstruction scheme to achieve a balance between the reconstruction algorithm control setting and the reconstruction quality/speed. In addition, dictionary weighting, online dictionary update, and/or point constraints may be used to improve the reconstruction quality.
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9.发明授权公开(公告)号：US09787316B2
公开(公告)日：2017-10-10
申请号：US15246580
申请日：2016-08-25
Applicant: MEDIATEK Inc.
Inventor： Yun-Shiang Shu
CPC classification number: H03M1/066 , H03M1/001 , H03M1/0673 , H03M1/145 , H03M1/68 , H03M3/338 , H03M3/344
Abstract: The invention provides a system for conversion between analog domain and digital domain with mismatch error shaping, including a DAC, a first injection circuit coupled to the DAC, and a second injection circuit coupled to the DAC. The DAC generates a first analog value in response to a first digital value, and generates a second analog value in response to a second digital value. The first injection circuit enables an analog injection value to be injected to the second analog value when the DAC generates the second analog value, wherein the analog injection value is converted from a digital injection value formed by a subset of bits of the first digital value. The second injection circuit injects the digital injection value to the second digital value, or combines the digital injection value and a related value obtained according to the second analog value.
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10.发明申请公开(公告)号：US20170230056A1
公开(公告)日：2017-08-10
申请号：US15497240
申请日：2017-04-26
Applicant: MEDIATEK Inc.
Inventor： Yun-Shiang Shu
CPC classification number: H03M1/066 , H03M1/001 , H03M1/0673 , H03M1/145 , H03M1/68 , H03M3/338 , H03M3/344
Abstract: The invention provides a system for conversion between analog domain and digital domain with mismatch error shaping, including a DAC, a first injection circuit coupled to the DAC, and a second injection circuit coupled to the DAC. The DAC generates a first analog value in response to a first digital value, and generates a second analog value in response to a second digital value. The first injection circuit enables an analog injection value to be injected to the second analog value when the DAC generates the second analog value, wherein the analog injection value is converted from a digital injection value formed by a subset of bits of the first digital value. The second injection circuit injects the digital injection value to the second digital value, or combines the digital injection value and a related value obtained according to the second analog value.
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