公开(公告)号：US20250045096A1

公开(公告)日：2025-02-06

申请号：US18918998

申请日：2024-10-17

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov ,  Samuel E. Bradshaw

IPC: G06F9/48 ,  G06F9/38 ,  G06F11/30 ,  G06F11/34 ,  G11C11/409

Abstract: Customized root processes for groups of applications in a computing device. A computing device (e.g., a mobile device) can monitor usage of applications. The device can then store data related to the usage of the applications, and group the applications into groups according to the stored data. The device can customize and execute a root process for a group of applications according to usage common to each application in the group. The device can generate patterns of prior executions shared amongst the applications in the group based on the stored data common to each application in the group, and execute the root process of the group according to the patterns. The device can receive a request to start an application from the group from a user of the device, and start the application upon receiving the request and by using the root process of the group of applications.

公开(公告)号：US20240231951A1

公开(公告)日：2024-07-11

申请号：US18612658

申请日：2024-03-21

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov

IPC: G06F9/50 ,  G06N20/00 ,  H04W88/08

CPC classification number: G06F9/5083 ,  G06N20/00 ,  H04W88/08

Abstract: Systems and methods for implementing shadow computations in base stations. The systems and methods can include a method including initiating, at a base station (such as a cellular base station), a shadow computation of a main computation executing for a mobile device. The main computation can include a computational task, and the shadow computation can be at least a part of or a derivative of the main computation. The method can also include executing, by the base station, the shadow computation.

公开(公告)号：US11934824B2

公开(公告)日：2024-03-19

申请号：US16841222

申请日：2020-04-06

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov ,  Sean S. Eilert ,  Sivagnanam Parthasarathy ,  Shivasankar Gunasekaran ,  Ameen D. Akel

IPC: G06F9/30 ,  G06F7/544

CPC classification number: G06F9/3001 ,  G06F7/5443 ,  G06F9/30032 ,  G06F9/30043

Abstract: Methods, apparatuses, and systems for in- or near-memory processing are described. Strings of bits (e.g., vectors) may be fetched and processed in logic of a memory device without involving a separate processing unit. Operations (e.g., arithmetic operations) may be performed on numbers stored in a bit-parallel way during a single sequence of clock cycles. Arithmetic may thus be performed in a single pass as numbers are bits of two or more strings of bits are fetched and without intermediate storage of the numbers. Vectors may be fetched (e.g., identified, transmitted, received) from one or more bit lines. Registers of a memory array may be used to write (e.g., store or temporarily store) results or ancillary bits (e.g., carry bits or carry flags) that facilitate arithmetic operations. Circuitry near, adjacent, or under the memory array may employ XOR or AND (or other) logic to fetch, organize, or operate on the data.

公开(公告)号：US11934798B2

公开(公告)日：2024-03-19

申请号：US16836773

申请日：2020-03-31

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov

IPC: G06F7/544 ,  G06F3/06 ,  G06F7/523 ,  G06N3/08

CPC classification number: G06F7/5443 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673 ,  G06F7/523 ,  G06N3/08

Abstract: The present disclosure is directed to systems and methods for a memory device such as, for example, a Processing-In-Memory Device that is configured to perform multiplication operations in memory using a popcount operation. A multiplication operation may include a summation of multipliers being multiplied with corresponding multiplicands. The inputs may be arranged in particular configurations within a memory array. Sense amplifiers may be used to perform the popcount by counting active bits along bit lines. One or more registers may accumulate results for performing the multiplication operations.

公开(公告)号：US20240086689A1

公开(公告)日：2024-03-14

申请号：US17903923

申请日：2022-09-06

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov

IPC: G06N3/04 ,  G06N3/063 ,  G06N3/08

CPC classification number: G06N3/049 ,  G06N3/063 ,  G06N3/08

Abstract: The disclosed embodiments include a memory array configured to store a membrane potential and a synaptic connection identifier of each of a plurality of neurons, a plurality of processors coupled to the memory array, the plurality of processors configured to: immediately perform a search and match operation in the memory array upon receiving a spike message identifying relevant synaptic connections in the memory array, generate a bitmask signifying a first source neuron identifier having a match to a second source neuron identifier in the memory array, perform a synaptic integration and a long-time depression computation on a subset of spike messages including the first spike message, update membrane potentials of the plurality of neurons upon receiving an indication that all the spike messages identified in a barrier message have been received in the memory array, generate a new spike message, and transmit the new spike message to a network.

公开(公告)号：US11693657B2

公开(公告)日：2023-07-04

申请号：US16717890

申请日：2019-12-17

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov ,  Sean S. Eilert ,  Sivagnanam Parthasarathy ,  Shivasankar Gunasekaran ,  Ameen D. Akel

IPC: G06F9/38 ,  G11C7/06 ,  G06F9/30 ,  G11C7/10 ,  G11C8/10

CPC classification number: G06F9/3001 ,  G06F9/3893 ,  G11C7/06 ,  G11C7/1096 ,  G11C8/10

Abstract: Methods, apparatuses, and systems for in- or near-memory processing are described. Strings of bits (e.g., vectors) may be fetched and processed in logic of a memory device without involving a separate processing unit. Operations (e.g., arithmetic operations) may be performed on numbers stored in a bit-serial way during a single sequence of clock cycles. Arithmetic may thus be performed in a single pass as numbers are bits of two or more strings of bits are fetched and without intermediate storage of the numbers. Vectors may be fetched (e.g., identified, transmitted, received) from one or more bit lines. Registers of the memory array may be used to write (e.g., store or temporarily store) results or ancillary bits (e.g., carry bits or carry flags) that facilitate arithmetic operations. Circuitry near, adjacent, or under the memory array may employ XOR or AND (or other) logic to fetch, organize, or operate on the data.

公开(公告)号：US11657002B2

公开(公告)日：2023-05-23

申请号：US17375455

申请日：2021-07-14

Applicant: Micron Technology, Inc.

Inventor： Samuel E. Bradshaw ,  Ameen D. Akel ,  Kenneth Marion Curewitz ,  Sean Stephen Eilert ,  Dmitri Yudanov

IPC: G06F12/1027 ,  H04W84/04

CPC classification number: G06F12/1027 ,  G06F2212/657 ,  G06F2212/68 ,  H04W84/042

Abstract: Systems, methods and apparatuses to accelerate accessing of borrowed memory over network connection are described. For example, a memory management unit (MMU) of a computing device can be configured to be connected both to the random access memory over a memory bus and to a computer network via a communication device. The computing device can borrow an amount of memory from a remote device over a network connection using the communication device; and applications running in the computing device can use virtual memory addresses mapped to the borrowed memory. When a virtual address mapped to the borrowed memory is used, the MMU translates the virtual address into a physical address and instruct the communication device to access the borrowed memory.

公开(公告)号：US20230153584A1

公开(公告)日：2023-05-18

申请号：US17529068

申请日：2021-11-17

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov

IPC: G06N3/04

CPC classification number: G06N3/049

Abstract: Systems, apparatus, and methods related to parallel processing in a spiking neural network are described. In some examples, parallel processors may compute a time delta vector based on post-synaptic timestamp vector and a current timestamp. The processors may calculate a long-term depression (LTD) value based on the time delta vector and load synaptic weights from memory based on at least the time delta vector. The processors may compute a second time delta vector using various inputs, such as a pre-synaptic timestamp vector, the current timestamp, and pre-synaptic timestamps. The processors may calculate a long-term potentiation (LTP) value based on the second time delta vector and adjust a current synaptic weight vector based on the LTD value and LTP value to generate an updated synaptic weight vector. The updated synaptic weight vector may be written to volatile memory (e.g., DRAM) or non-volatile (e.g., NAND Flash).

公开(公告)号：US11614797B2

公开(公告)日：2023-03-28

申请号：US16675171

申请日：2019-11-05

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov ,  Samuel E. Bradshaw

IPC: G06F3/01 ,  G06F3/0482 ,  G06F3/16 ,  G06F3/0487 ,  G02B27/01 ,  G06V40/19

Abstract: An apparatus having a computing device and a user interface—such as a user interface having a display that can provide a graphical user interface (GUI). The apparatus also includes a camera, and a processor in the computing device. The camera can be connected to the computing device and/or the user interface, and the camera can be configured to capture pupil location and/or eye movement of a user. The processor can be configured to: identify a visual focal point of the user relative to the user interface based on the captured pupil location, and/or identify a type of eye movement of the user (such as a saccade) based on the captured eye movement. The processor can also be configured to control parameters of the user interface based at least partially on the identified visual focal point and/or the identified type of eye movement.

公开(公告)号：US11599384B2

公开(公告)日：2023-03-07

申请号：US16592529

申请日：2019-10-03

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov ,  Samuel E. Bradshaw

IPC: G06F9/46 ,  G06F9/48 ,  G11C11/409 ,  G06F11/30 ,  G06F9/38

Abstract: A computing device (e.g., a mobile device) can execute a root process of an application to an initial point according to patterns of prior executions of the application. The root process can be one of many respective customized root processes of individual applications in the computing device. The device can receive a request to start the application from a user of the device. And, the device can start the application upon receiving the request to start the application and by using the root process of the application. At least one of the executing, receiving, or starting can be performed by an operating system in the device. The device can also fork the root process of the application into multiple processes, and can start upon receiving the request to start the application and by using at least one of the multiple processes according to the request to start the application.