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公开(公告)号：US20250087292A1
公开(公告)日：2025-03-13
申请号：US18953302
申请日：2024-11-20
Applicant: Micron Technology, Inc.
Inventor： Guang Hu
Abstract: A method includes identifying a read level offset assigned to a final bin in a scan order defined for a set of bins, identifying a set of bit error metric values by performing, using the read level offset, a scan operation with respect to a block of memory cells of the memory array, determining whether a final bit error metric value of the set of bit error metric values is greater than or equal to a threshold value, in response to determining that the final bit error metric value is greater than or equal to the threshold value, identifying a lowest bit error metric value of the set of bit error metric values, and selecting, from the set of bins, a bin having an assigned read level offset corresponding to the lowest bit error metric value.
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公开(公告)号：US12079481B2
公开(公告)日：2024-09-03
申请号：US17898333
申请日：2022-08-29
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Chun Sum Yeung , Deping He , Ting Luo , Guang Hu , Jonathan S. Parry
IPC: G06F3/06
CPC classification number: G06F3/0611 , G06F3/0653 , G06F3/0679
Abstract: Described are systems and methods related to a memory block erase protocol. An example system includes a memory device having a memory array including a plurality of memory cells. The system further includes a processing device coupled to the memory device. The processing device is to determine a value of a metric associated with the memory array. Responsive to determine that the value of the metric is below a predetermined threshold, the processing device is further to initiate an erase protocol of the memory device. The processing device is further to erase sets of memory cells associated with one or more memory blocks of the memory array. The processing device is further to receive a programming command directed to the first set of memory cells. The processing device is further to perform a programming operation with respect to a set of memory cells responsive to receiving the programming command.
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3.发明公开公开(公告)号：US20240071547A1
公开(公告)日：2024-02-29
申请号：US18231514
申请日：2023-08-08
Applicant: Micron Technology, Inc.
Inventor： Guang Hu , Nicola Ciocchini
IPC: G11C29/32
CPC classification number: G11C29/32
Abstract: A memory device includes a memory array and control logic operatively coupled with the memory array to perform operations including maintaining a set of bins, each bin of the set of bins defining a respective grouping of memory arrays based on elapsed time since programming, wherein each bin of the set of bins is assigned a respective read level offset to achieve a bit error rate satisfying a threshold condition for an error correction decoder throughput specification, receiving a request to perform a read operation addressing the memory array, and causing the read operation to be performed based on the set of bins.
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公开(公告)号：US12277984B2
公开(公告)日：2025-04-15
申请号：US18231514
申请日：2023-08-08
Applicant: Micron Technology, Inc.
Inventor： Guang Hu , Nicola Ciocchini
Abstract: A memory device includes a memory array and control logic operatively coupled with the memory array to perform operations including maintaining a set of bins, each bin of the set of bins defining a respective grouping of memory arrays based on elapsed time since programming, wherein each bin of the set of bins is assigned a respective read level offset to achieve a bit error rate satisfying a threshold condition for an error correction decoder throughput specification, receiving a request to perform a read operation addressing the memory array, and causing the read operation to be performed based on the set of bins.
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公开(公告)号：US12183413B2
公开(公告)日：2024-12-31
申请号：US17898725
申请日：2022-08-30
Applicant: Micron Technology, Inc.
Inventor： Guang Hu
Abstract: A method includes, in response to detecting a power on event, selecting a block from a set of blocks, causing a first scan to be performed using a set of read level offsets to select, from a set of bins in accordance with a scan order, a first bin assigned with a first read level offset resulting in a first bit error metric value, in response to determining that the first bin is not an initial bin of the scan order, causing, using a second read level offset assigned to a second bin, a second scan to be performed to obtain a second bit error metric value, wherein the second bin immediately precedes the first bin in the scan order, and selecting, based on first bit error metric value and the second bit error metric value, an optimal bin from the set of bins.
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Patent Agency Ranking
公开(公告)号：US11886736B2
公开(公告)日：2024-01-30
申请号：US17966391
申请日：2022-10-14
Applicant: Micron Technology, Inc.
Inventor： Guang Hu
IPC: G06F3/06
CPC classification number: G06F3/0655 , G06F3/0604 , G06F3/0679
Abstract: A method includes determining respective memory access counts of a plurality of blocks of non-volatile memory cells that are grouped into a plurality of respective groups, comparing the respective memory access counts to respective memory access thresholds, determining a respective memory access count of a block of non-volatile memory cells exceeds a respective memory access threshold, and performing a media scan operation on the block of non-volatile memory cells.
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公开(公告)号：US20230245695A1
公开(公告)日：2023-08-03
申请号：US17649885
申请日：2022-02-03
Applicant: Micron Technology, Inc.
IPC: G11C11/4099 , G11C11/4074 , G11C11/408 , G11C11/4076 , G11C11/4096
CPC classification number: G11C11/4099 , G11C11/4074 , G11C11/4085 , G11C11/4076 , G11C11/4096
Abstract: Methods, systems, and devices for reference voltage adjustment for word line groups are described. In some examples, one or more components of a memory system may determine a duration that data has been stored to one or more memory cells. Based on the duration, a voltage value of one or more reference voltages may be adjusted accordingly. For example, a voltage value of one or more reference voltages may be adjusted based on the duration. Moreover, the reference voltage values may be adjusted differently in response to the memory cells having stored data for a relatively longer duration, as opposed to memory cells that have stored data for a relatively shorter duration. The adjusted reference voltages may be used during a subsequent read operation. The voltage value of the one or more reference voltages may be adjusted on a word-line group by word-line group basis.
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公开(公告)号：US11599300B2
公开(公告)日：2023-03-07
申请号：US17234095
申请日：2021-04-19
Applicant: Micron Technology, Inc.
Inventor： Chun Sum Yeung , Guang Hu , Ting Luo , Tao Liu
IPC: G06F3/06
Abstract: A method includes performing a first read operation involving a set of memory cells using a first voltage, determining a quantity of bits associated with the set of memory cells based on the first read operation, performing a second read operation involving the set of memory cells using a second voltage that is greater than the first voltage when the quantity of bits is above a threshold quantity of bits for the set of memory cells, and performing the second read operation involving the set of memory cells using a third voltage that is less than the first voltage when the quantity of bits is below the threshold quantity of bits for the set of memory cells.
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公开(公告)号：US11500578B2
公开(公告)日：2022-11-15
申请号：US17234227
申请日：2021-04-19
Applicant: Micron Technology, Inc.
Inventor： Guang Hu
IPC: G06F3/06
Abstract: A method includes determining respective memory access counts of a plurality of blocks of non-volatile memory cells that are grouped into a plurality of respective groups, comparing the respective memory access counts to respective memory access thresholds, determining a respective memory access count of a block of non-volatile memory cells exceeds a respective memory access threshold, and performing a media scan operation on the block of non-volatile memory cells.
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公开(公告)号：US20250130894A1
公开(公告)日：2025-04-24
申请号：US18776314
申请日：2024-07-18
Applicant: Micron Technology, Inc.
Inventor： Lei Lin , Guang Hu , Chun Sum Yeung , Dongxiang Liao , Xiangang Luo
IPC: G06F11/10
Abstract: Various embodiments provide for dynamically enabling and disabling foreground scans of blocks of a memory device, which can be part of a memory sub-system. For instance, some embodiments provide an improved methodology for triggering foreground media scans of blocks of a memory device without disturbing a maximum idea time of background media scans of blocks of the memory device.
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