公开(公告)号：US20250014640A1

公开(公告)日：2025-01-09

申请号：US18768922

申请日：2024-07-10

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Jeffrey E. Koelling ,  Hari Giduturi ,  Riccardo Muzzetto ,  Corrado Villa

IPC: G11C13/00

Abstract: Methods, systems, and devices for decoder architecture for memory device are described. An apparatus includes a memory array having a memory cell and an access line coupled with the cell and a decoder having a first stage and a second stage. The decoder supplying a first voltage during a first access operation and a second voltage during a second access operation to the access line. The second stage of the decoder includes a first transistor that supplies the first voltage based on a third voltage at the source of the first transistor exceeding a fourth voltage at a gate of the first transistor and a first threshold voltage. The second stage includes a second transistor that supplies the second voltage based on a fifth voltage at a gate of the second transistor exceeding a sixth voltage at the source of the second transistor and a second threshold voltage.

公开(公告)号：US20240339149A1

公开(公告)日：2024-10-10

申请号：US18749412

申请日：2024-06-20

Applicant: Micron Technology, Inc.

Inventor： Joseph Michael McCrate ,  Robert John Gleixner ,  Hari Giduturi ,  Ramin Ghodsi

IPC: G11C11/408 ,  G11C11/4091 ,  G11C13/00

CPC classification number: G11C11/4087 ,  G11C11/4091 ,  G11C13/0002 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0045 ,  G11C2211/4013

Abstract: The application relates to an architecture that allows for less precision of demarcation read voltages by combining two physical memory cells into a single logical bit. Reciprocal binary values may be written into the two memory cells that make up a memory pair. When activated using bias circuitry and address decoders the memory cell pair creates current paths having currents that may be compared to detect a differential signal. The application is also directed to writing and reading memory cell pairs.

公开(公告)号：US12008236B2

公开(公告)日：2024-06-11

申请号：US17461035

申请日：2021-08-30

Applicant: Micron Technology, Inc.

Inventor： Hari Giduturi ,  Bret Addison Johnson

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0655 ,  G06F3/0679

Abstract: A device includes a first memory die and a second memory die directly coupled to the first memory die via a first bus. The device also includes a second bus directly coupled to the first memory die. The first memory die includes a first trim circuit that when in operation adjusts a delay of signal transmission by the first memory die to a first value, while the second memory die comprises a second trim circuit that when in operation adjusts a delay of signal transmission by the second memory die to a second value.

公开(公告)号：US20230402094A1

公开(公告)日：2023-12-14

申请号：US18457188

申请日：2023-08-28

Applicant: Micron Technology, Inc.

Inventor： Hari Giduturi

IPC: G11C13/00 ,  G11C11/16

CPC classification number: G11C13/003 ,  G11C13/0023 ,  G11C11/1659 ,  G11C11/1653

Abstract: Methods and systems include memory devices with multiple access lines arranged in an array to form a multiple intersections. Memory cells are located at the intersections of the multiple access lines. Decoders are configured to drive the multiple memory cells via the multiple access lines. Variable biasing circuitry may bias a voltage on an access line of the multiple access lines to change a variable ramp rate of the voltage on the access line. A control circuit is configured to determine a memory cell of the multiple memory cells to be activated. Based at least in part on a distance from the memory cell to a corresponding decoder, the control circuit may set the variable ramp rate of the biasing circuitry.

公开(公告)号：US20230117173A1

公开(公告)日：2023-04-20

申请号：US17506421

申请日：2021-10-20

Applicant: Micron Technology, Inc.

Inventor： Hari Giduturi

IPC: G11C29/42 ,  G11C29/12 ,  G11C7/10

Abstract: Memory devices may perform read operations and write operations with different bit error correction rates to satisfy a bit error correction rate. However, improving the bit error correction rate of the memory device using a single type of read command and/or write commands may result in longer read and write commands. Moreover, using longer read and write commands may result in undesirable higher memory power consumption and may reduce memory throughput. Accordingly, memory operations are described that may use combination of commands with increased bit error correction capability and reduced bit error correction capability. For example, the read operations may use multiple (e.g., at least two) sets or groupings of read commands and the write operations may use multiple (e.g., at least two) sets or groupings of write commands.

公开(公告)号：US20220215877A1

公开(公告)日：2022-07-07

申请号：US17702562

申请日：2022-03-23

Applicant: Micron Technology, Inc.

Inventor： Hari Giduturi

IPC: G11C13/00 ,  G06F9/30

Abstract: A memory system may include multiple memory cells to store logical data and cycle tracking circuitry to track a number of cycles associated the memory cells. The cycles may be representative of one or more past accesses of the memory cells. The memory system may also include control circuitry to access the memory cells. Accessing of the memory cell may include a read operation, a write operation, or both. During the accessing of the memory cell, the control circuitry may determine a voltage parameter of the access based at least in part on the tracked number of cycles.

公开(公告)号：US20220172778A1

公开(公告)日：2022-06-02

申请号：US17108763

申请日：2020-12-01

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Jeffrey E. Koelling ,  Hari Giduturi ,  Riccardo Muzzetto ,  Corrado Villa

IPC: G11C13/00

Abstract: Methods, systems, and devices for decoder architecture for memory device are described. An apparatus includes a memory array having a memory cell and an access line coupled with the cell and a decoder having a first stage and a second stage. The decoder supplying a first voltage during a first access operation and a second voltage during a second access operation to the access line. The second stage of the decoder includes a first transistor that supplies the first voltage based on a third voltage at the source of the first transistor exceeding a fourth voltage at a gate of the first transistor and a first threshold voltage. The second stage includes a second transistor that supplies the second voltage based on a fifth voltage at a gate of the second transistor exceeding a sixth voltage at the source of the second transistor and a second threshold voltage.

公开(公告)号：US20220068376A1

公开(公告)日：2022-03-03

申请号：US17008254

申请日：2020-08-31

Applicant: Micron Technology, Inc.

Inventor： Hari Giduturi

IPC: G11C13/00 ,  G06F3/06

Abstract: Memory device systems and methods for using methods include multiple access lines arranged in a grid. Multiple memory cells are located at intersections of the access lines in the grid. Multiple drivers are included with each configured to transmit a corresponding signal to respective memory cells of the multiple memory cells. Remapping circuitry is configured to remap a near memory cell of the multiple memory cells to a far memory cell of the multiple memory cells. The near memory cell is relatively nearer to a respective driver of the multiple drivers than the far memory cell is to a respective driver of the multiple drivers.

公开(公告)号：US20210118501A1

公开(公告)日：2021-04-22

申请号：US16660594

申请日：2019-10-22

Applicant: Micron Technology, Inc.

Inventor： Mingdong Cui ,  Nathan Joseph Sirocka ,  Hari Giduturi

IPC: G11C13/00

Abstract: An integrated circuit memory device having: a memory cell; and a voltage driver of depletion type connected to the memory cell. In a first polarity, the voltage driver is powered by a negative voltage relative to ground to drive a negative selection voltage or a first de-selection voltage; In a second polarity, the voltage driver is powered by a positive voltage relative to ground to drive a positive selection voltage or a second de-selection voltage. The voltage driver is configured to transition between the first polarity and the second polarity. During the transition, the voltage driver is configured to have a control voltage swing for outputting de-selection voltages smaller than a control voltage swing for output selection voltages.

公开(公告)号：US10410718B2

公开(公告)日：2019-09-10

申请号：US16190563

申请日：2018-11-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Fabio Pellizzer ,  Hari Giduturi ,  Mingdong Cui

IPC: G11C11/00 ,  G11C13/00 ,  G11C29/50

Abstract: Apparatuses and methods for limiting current in threshold switching memories are disclosed. An example apparatus may include a plurality of first decoder circuits, a plurality of second decoder circuits, an array of memory cells, and a control circuit. Each memory cell of the array of memory cells may be cells coupled to a pair of first decoder circuits of the plurality of first decoder circuits, and further coupled to a pair of second decoder circuits of the plurality of second decoder circuits. The control circuit may be coupled to the plurality of first decoder circuits and the plurality of second decoder circuits, and the control circuit may be configured to activate a first one of the pair of first decoder circuits coupled to a memory cell of the array of memory cells before a second one of the pair of first decoder circuits, and further configured to activate a first one of the pair of second decoder circuits coupled to the memory cell of the array of memory cells before a second one of the pair of second decoder circuits to access the a memory cell.