公开(公告)号：US20240194256A1

公开(公告)日：2024-06-13

申请号：US18373490

申请日：2023-09-27

Applicant: Micron Technology, Inc.

Inventor： Brenton P. Van Leeuwen ,  Mingdong Cui ,  Fatma Arzum Simsek-Ege

IPC: G11C13/00

CPC classification number: G11C13/0028 ,  G11C13/0038

Abstract: Systems, methods and apparatus are provided for word line drivers for memory devices. For instance, an apparatus can include sets of word lines, each word line of the sets of word lines configured to access a respective set of one or more memory cells, sets of digit lines, where each word line couples a memory cell of the set of one or more memory cells with each digit line within the sets of digit lines, and a plurality of resistors coupled to the sets of word lines.

公开(公告)号：US11967373B2

公开(公告)日：2024-04-23

申请号：US17831311

申请日：2022-06-02

Applicant: Micron Technology, Inc.

Inventor： Vijayakrishna J. Vankayala ,  Hari Giduturi ,  Jeffrey E. Koelling ,  Mingdong Cui ,  Ramachandra Rao Jogu

IPC: G11C13/00 ,  H03K19/20

CPC classification number: G11C13/0023 ,  G11C13/0004 ,  G11C2213/15 ,  H03K19/20

Abstract: The present disclosure includes apparatuses, methods, and systems for pre-decoder circuitry. An embodiment includes a memory array including a plurality of memory cells, decoder circuitry coupled to the memory array, wherein the decoder circuitry comprises a p-type transistor having a first gate, a first n-type transistor having a second gate, and a second n-type transistor having a third gate, and pre-decoder circuitry configured to provide a bias condition for the first gate, the second gate, and the third gate to provide a selection signal to one of the plurality of memory cells, wherein the bias condition comprises zero volts for the first gate, the second gate, and the third gate for a positive configuration for the memory cells and a negative voltage for the third gate and zero volts for the first gate and the second gate for a negative configuration for the memory cells.

公开(公告)号：US20240071465A1

公开(公告)日：2024-02-29

申请号：US17821645

申请日：2022-08-23

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Mingdong Cui ,  Richard E. Fackenthal

IPC: G11C11/408 ,  G11C5/02 ,  G11C11/4091

CPC classification number: G11C11/4085 ,  G11C5/025 ,  G11C11/4091

Abstract: Methods, systems, and devices for structures for word line multiplexing in three-dimensional memory arrays are described. A memory die may include circuitry for access line multiplexing in regions adjacent to or between staircase regions. For example, a multiplexing region may include, for each word line of a stack of word lines, a respective first portion of a semiconductor material and a respective second portion of the semiconductor material, and may also include a gate material operable to modulate a conductivity between the first portions and the second portions. Each word line may be coupled with the respective first portion of the semiconductor material, such that biasing of the gate material may couple the word lines with the respective second portion of the semiconductor material. Such features may support various techniques for multiplexing associated with the stack of word lines, or among multiple stacks of word lines, or both.

公开(公告)号：US20240071423A1

公开(公告)日：2024-02-29

申请号：US17893681

申请日：2022-08-23

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Mingdong Cui ,  Richard E. Facekenthal

IPC: G11C5/02 ,  G11C5/06 ,  G11C8/14 ,  H01L27/108

CPC classification number: G11C5/025 ,  G11C5/063 ,  G11C8/14 ,  H01L27/10891

Abstract: Methods, systems, and devices for structures for word line multiplexing in three-dimensional memory arrays are described. A memory die may include circuitry for access line multiplexing in regions adjacent to or between staircase regions. For example, a multiplexing region may include, for each word line of a stack of word lines, a respective first portion of a semiconductor material and a respective second portion of the semiconductor material, and may also include one or more gate material portions operable to modulate a conductivity between respective first and second portions. Each word line may be coupled with the respective first portion of the semiconductor material, such that biasing of the gate material portions may couple the word lines with the respective second portion of the semiconductor material. Such features may support various techniques for multiplexing associated with the stack of word lines, or among multiple stacks of word lines, or both.

公开(公告)号：US20230395145A1

公开(公告)日：2023-12-07

申请号：US17831311

申请日：2022-06-02

Applicant: Micron Technology, Inc.

Inventor： Vijayakrishna J. Vankayala ,  Hari Giduturi ,  Jeffrey E. Koelling ,  Mingdong Cui ,  Ramachandra Rao Jogu

IPC: G11C13/00

CPC classification number: G11C13/0023 ,  G11C13/0004 ,  H03K19/20

Abstract: The present disclosure includes apparatuses, methods, and systems for pre-decoder circuitry. An embodiment includes a memory array including a plurality of memory cells, decoder circuitry coupled to the memory array, wherein the decoder circuitry comprises a p-type transistor having a first gate, a first n-type transistor having a second gate, and a second n-type transistor having a third gate, and pre-decoder circuitry configured to provide a bias condition for the first gate, the second gate, and the third gate to provide a selection signal to one of the plurality of memory cells, wherein the bias condition comprises zero volts for the first gate, the second gate, and the third gate for a positive configuration for the memory cells and a negative voltage for the third gate and zero volts for the first gate and the second gate for a negative configuration for the memory cells.

公开(公告)号：US20190341919A1

公开(公告)日：2019-11-07

申请号：US16517000

申请日：2019-07-19

Applicant: Micron Technology, Inc.

Inventor： Mingdong Cui ,  Hari Giduturi

IPC: H03K19/0185 ,  H03K5/003 ,  H03K17/10

Abstract: Methods, systems, and devices for shifting voltage levels of electrical signals and more specifically for boosted high-speed level shifting are described. A boosted level shifter may include a driver circuit that generates a drive signal having a greater voltage swing than an input signal, and the drive signal may drive the gate of a pull-up transistor within the boosted level shifter. The lower bound of the drive signal may in some cases be a negative voltage. Driving the pull-up transistor with a drive signal having a greater voltage swing than the input signal may improve the operational speed and current-sourcing capability of the pull-up transistor, which may provide speed and efficiency benefits.

公开(公告)号：US10153040B2

公开(公告)日：2018-12-11

申请号：US15828402

申请日：2017-11-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Fabio Pellizzer ,  Hari Giduturi ,  Mingdong Cui

IPC: G11C11/00 ,  G11C13/00 ,  G11C29/50

Abstract: Apparatuses and methods for limiting current in threshold switching memories are disclosed. An example apparatus may include a plurality of first decoder circuits, a plurality of second decoder circuits, an array of memory cells, and a control circuit. Each memory cell of the array of memory cells may be cells coupled to a pair of first decoder circuits of the plurality of first decoder circuits, and further coupled to a pair of second decoder circuits of the plurality of second decoder circuits. The control circuit may be coupled to the plurality of first decoder circuits and the plurality of second decoder circuits, and the control circuit may be configured to activate a first one of the pair of first decoder circuits coupled to a memory cell of the array of memory cells before a second one of the pair of first decoder circuits, and further configured to activate a first one of the pair of second decoder circuits coupled to the memory cell of the array of memory cells before a second one of the pair of second decoder circuits to access the a memory cell.

公开(公告)号：US20240304233A1

公开(公告)日：2024-09-12

申请号：US18667802

申请日：2024-05-17

Applicant: Micron Technology, Inc.

Inventor： Jin Seung Son ,  Mingdong Cui

IPC: G11C11/408 ,  G11C11/4074 ,  G11C11/4093 ,  G11C11/4096

CPC classification number: G11C11/4087 ,  G11C11/4074 ,  G11C11/4093 ,  G11C11/4096

Abstract: The disclosure includes apparatuses, methods, and systems for pre-decoder circuitry. An embodiment includes a memory array including a plurality of memory cells, decoder circuitry coupled to the array and comprising a first and second n-type transistor having a first and second gate, respectively, and pre-decoder circuity to provide a bias condition for the first and second gate to provide a selection signal to one of the cells. The bias condition comprises a positive voltage for the first gate and a negative voltage for the second gate for a positive memory cell configuration, and zero volts for the first gate and the negative voltage for the second gate for a negative memory cell configuration. The pre-decoder circuitry comprises first pre-decoder circuitry to provide the positive voltage for the first gate and the zero volts for the second gate and second pre-decoder circuitry to provide the negative voltage for the second gate.

公开(公告)号：US12051459B2

公开(公告)日：2024-07-30

申请号：US17893654

申请日：2022-08-23

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Mingdong Cui

IPC: G11C16/10 ,  G11C11/408 ,  H10B80/00

CPC classification number: G11C11/4085 ,  G11C11/4087 ,  H10B80/00

Abstract: Methods, systems, and devices for word line drivers for multiple-die memory devices are described. A memory device may include a first semiconductor die associated with at least memory cells and corresponding access lines of the memory device, and a second semiconductor die associated with at least access line driver circuitry of the memory device. The second semiconductor die may be located in contact with or otherwise adjacent to the first semiconductor die, and electrical contacts may be formed to couple the access line driver circuitry of the second semiconductor die with the access line conductors of the first semiconductor die. For example, cavities may be formed through the second semiconductor die and at least a portion of the first semiconductor die, and the electrical contacts may be formed between the semiconductor dies at least in part from forming a conductive material in the cavities.

公开(公告)号：US11798622B2

公开(公告)日：2023-10-24

申请号：US17865248

申请日：2022-07-14

Applicant: Micron Technology, Inc.

Inventor： Joemar Sinipete ,  John Christopher Sancon ,  Mingdong Cui

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/0097 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0033 ,  G11C13/0069 ,  G11C2013/0045 ,  G11C2013/0078

Abstract: Methods, systems, and devices for a refresh operation of a memory cell are described. A memory device may include a plurality of rows of memory cells. Each row of memory cells may undergo a quantity of access operations (e.g., read operations, write operations). During a read operation, a logic state of one or more memory cells may be determined by applying a read pulse having a first polarity. Based on the one or more memory cells storing a particular logic state (e.g., a first logic state), a refresh operation may be performed. During a refresh operation, a refresh pulse having a second polarity (e.g., a different polarity than the first polarity) may be applied to the one or more memory cells.