公开(公告)号：US20250130718A1

公开(公告)日：2025-04-24

申请号：US18889047

申请日：2024-09-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Antonino Caprì ,  Graziano Mirichigni ,  Marco Sforzin ,  Bryan David Kerstetter ,  John David Porter

IPC: G06F3/06

Abstract: A system performs operations including: storing a first value in a first memory location used for selecting a sub-channel of a plurality of sub-channels in a communication channel, each of the plurality of sub-channels corresponding to one or more memory components of a plurality of memory components of the memory device, wherein the first value specifies that a sub-channel selecting function is enabled; receiving, through the communication channel, a command directed to the memory device; responsive to receiving the command, storing a second value in a second memory location, wherein the second value is obtained from the command; determining that the second value matches a third value stored in a third memory location, wherein the third value stored in the third memory location comprises a preset value corresponding to a first component of the plurality of components of the memory device; and executing, by the first component, the command.

公开(公告)号：US20230222042A1

公开(公告)日：2023-07-13

申请号：US17575399

申请日：2022-01-13

Applicant: Micron Technology, Inc.

Inventor： Angelo Visconti ,  John David Porter

IPC: G06F11/30 ,  G11C5/14

CPC classification number: G06F11/3058 ,  G06F11/3055 ,  G06F11/3037 ,  G11C5/14

Abstract: Systems and methods described herein may enable memory maintenance operations to be performed on a memory device in compliance with a time interval having a duration based on a temperature of the memory device. A system may include a memory device and a memory controller communicatively coupled to the memory device. The memory controller may receive a temperature measurement indicative of a present temperature of the memory device and determine a memory management interval based on the temperature measurement. The memory controller may perform a memory management operation based on the memory management interval. Sometimes, the memory controller powers on the memory device to perform the memory management operation on the memory device.

公开(公告)号：US20220351757A1

公开(公告)日：2022-11-03

申请号：US17747499

申请日：2022-05-18

Applicant: Micron Technology, Inc.

Inventor： John David Porter ,  Suryanarayana B. Tatapudi

IPC: G11C7/04 ,  G06F3/06 ,  G11C11/22

Abstract: Methods, systems, and devices are described for adjusting parameters of channel drivers based on temperature when a calibration component is unavailable. A memory device may determine whether a calibration component is available for use by the memory device. If not, the memory device may select an impedance setting for the driver that is based on an operating temperature of the memory device. A device or system may identify a temperature of a memory device, identify that a calibration component is unavailable to adjust a parameter of a driver of a data channel, select a value of the parameter based on the temperature and on identifying that the calibration component is unavailable, adjust the parameter of the driver of the data channel to the selected value, and transmit, by the driver operating using the selected value of the parameter, a signal over the channel.

公开(公告)号：US20220308757A1

公开(公告)日：2022-09-29

申请号：US17721160

申请日：2022-04-14

Applicant: Micron Technology, Inc.

Inventor： Suryanarayana B. Tatapudi ,  John David Porter ,  Jaeil Kim ,  Mijo Kim

IPC: G06F3/06 ,  G06F13/16 ,  G11C7/10

Abstract: Techniques for configurable link interfaces for a memory device are described. In some examples, memory devices may require periodic link training to support data transfer with a host device at relatively fast rates. However, in some managed memory applications, memory dies of a memory device may have integrated controllers that do not support such link training, and accordingly may not support some clock rates or data rates. To support data transfers between a host device and a memory device at relatively fast clock rates or data rates without link training, a memory die may be fabricated with a configurable link interface that can support different mappings between components and operation according to different clock rates or data rates. In some examples, a memory die may be fabricated in a manner that supports configurable mappings between an array and a data channel interface that are operable according to different multiplexing and serialization.

公开(公告)号：US11355165B2

公开(公告)日：2022-06-07

申请号：US16859417

申请日：2020-04-27

Applicant: Micron Technology, Inc.

Inventor： John David Porter ,  Suryanarayana B. Tatapudi

IPC: G11C7/04 ,  G06F3/06 ,  G11C11/22

Abstract: Methods, systems, and devices are described for adjusting parameters of channel drivers based on temperature when a calibration component is unavailable. A memory device may determine whether a calibration component is available for use by the memory device. If not, the memory device may select an impedance setting for the driver that is based on an operating temperature of the memory device. A device or system may identify a temperature of a memory device, identify that a calibration component is unavailable to adjust a parameter of a driver of a data channel, select a value of the parameter based on the temperature and on identifying that the calibration component is unavailable, adjust the parameter of the driver of the data channel to the selected value, and transmit, by the driver operating using the selected value of the parameter, a signal over the channel.

公开(公告)号：US11307771B2

公开(公告)日：2022-04-19

申请号：US16925773

申请日：2020-07-10

Applicant: Micron Technology, Inc.

Inventor： Suryanarayana B. Tatapudi ,  John David Porter ,  Jaeil Kim ,  Mijo Kim

IPC: G06F3/06 ,  G06F13/16 ,  G11C7/10

Abstract: Techniques for configurable link interfaces for a memory device are described. In some examples, memory devices may require periodic link training to support data transfer with a host device at relatively fast rates. However, in some managed memory applications, memory dies of a memory device may have integrated controllers that do not support such link training, and accordingly may not support some clock rates or data rates. To support data transfers between a host device and a memory device at relatively fast clock rates or data rates without link training, a memory die may be fabricated with a configurable link interface that can support different mappings between components and operation according to different clock rates or data rates. In some examples, a memory die may be fabricated in a manner that supports configurable mappings between an array and a data channel interface that are operable according to different multiplexing and serialization.

公开(公告)号：US11243554B1

公开(公告)日：2022-02-08

申请号：US16983811

申请日：2020-08-03

Applicant: Micron Technology, Inc.

Inventor： Anupriya Chakraborty ,  John David Porter ,  Alan John Wilson

IPC: G05F3/20 ,  G11C5/14

Abstract: Techniques for providing temperature trim codes to multiple reference circuits of an integrated circuit are provided. In an example, a string of primary latch circuits can provide a set of pre-defined temperature trim codes to a multiplexer in response to a token of a series of tokens. The multiplexer can provide two trim of the trim codes to an interpolator based on a temperature reading of the integrated circuit. The interpolator can provide an interpolated trim code and the trim code can be distributed to a reference circuit based on the token.

公开(公告)号：US20160276017A1

公开(公告)日：2016-09-22

申请号：US15170785

申请日：2016-06-01

Applicant: MICRON TECHNOLOGY, INC.

Inventor： John David Porter ,  Gi-Hong Kim

IPC: G11C11/406 ,  G11C11/408

CPC classification number: G11C11/40615 ,  G11C5/147 ,  G11C8/08 ,  G11C8/10 ,  G11C11/402 ,  G11C11/406 ,  G11C11/4085 ,  G11C2211/4065 ,  G11C2211/4067

Abstract: Apparatuses, memory section control circuits, and methods of refreshing memory are disclosed. An example apparatus includes a plurality of memory sections and a plurality of memory section control circuits. Each memory section control circuit is coupled to a respective one of the plurality of memory sections and includes a plurality of access line drivers, each of which includes a plurality of transistors having common coupled gates. During an operation of the apparatus a first voltage is provided to the commonly coupled gates of the transistors of at least some of the access line drivers of the memory section control circuit coupled to an active memory section and a second voltage is provided to the commonly coupled gates of the transistors of the access line drivers of the memory section control circuit coupled to an inactive memory section control circuit, wherein the first voltage is greater than the second voltage.

公开(公告)号：US09368184B2

公开(公告)日：2016-06-14

申请号：US14505717

申请日：2014-10-03

Applicant: Micron Technology, Inc.

Inventor： John David Porter ,  Gi-Hong Kim

IPC: G11C7/00 ,  G11C11/402 ,  G11C8/08 ,  G11C8/10 ,  G11C11/406 ,  G11C11/408 ,  G11C5/14

CPC classification number: G11C11/40615 ,  G11C5/147 ,  G11C8/08 ,  G11C8/10 ,  G11C11/402 ,  G11C11/406 ,  G11C11/4085 ,  G11C2211/4065 ,  G11C2211/4067

Abstract: Apparatuses, memory section control circuits, and methods of refreshing memory are disclosed. An example apparatus includes a plurality of memory sections and a plurality of memory section control circuits. Each memory section control circuit is coupled to a respective one of the plurality of memory sections and includes a plurality of access line drivers, each of which includes a plurality of transistors having common coupled gates. During an operation of the apparatus a first voltage is provided to the commonly coupled gates of the transistors of at least some of the access line drivers of the memory section control circuit coupled to an active memory section and a second voltage is provided to the commonly coupled gates of the transistors of the access line drivers of the memory section control circuit coupled to an inactive memory section control circuit, wherein the first voltage is greater than the second voltage.

公开(公告)号：US20150023121A1

公开(公告)日：2015-01-22

申请号：US14505717

申请日：2014-10-03

Applicant: Micron Technology, Inc.

Inventor： John David Porter ,  Gi-Hong Kim

IPC: G11C11/402 ,  G11C8/10 ,  G11C8/08 ,  G11C5/14 ,  G11C11/408

CPC classification number: G11C11/40615 ,  G11C5/147 ,  G11C8/08 ,  G11C8/10 ,  G11C11/402 ,  G11C11/406 ,  G11C11/4085 ,  G11C2211/4065 ,  G11C2211/4067

Abstract: Apparatuses, memory section control circuits, and methods of refreshing memory are disclosed. An example apparatus includes a plurality of memory sections and a plurality of memory section control circuits. Each memory section control circuit is coupled to a respective one of the plurality of memory sections and includes a plurality of access line drivers, each of which includes a plurality of transistors having common coupled gates. During an operation of the apparatus a first voltage is provided to the commonly coupled gates of the transistors of at least some of the access line drivers of the memory section control circuit coupled to an active memory section and a second voltage is provided to the commonly coupled gates of the transistors of the access line drivers of the memory section control circuit coupled to an inactive memory section control circuit, wherein the first voltage is greater than the second voltage.

Abstract translation: 公开了设备，存储器部分控制电路和刷新存储器的方法。 示例性设备包括多个存储器部分和多个存储器部分控制电路。 每个存储器部分控制电路耦合到多个存储器部分中的相应一个，并且包括多个存取线驱动器，每个存取线驱动器包括具有公共耦合栅极的多个晶体管。 在装置的操作期间，将第一电压提供给耦合到有源存储器部分的存储器部分控制电路的至少一些存取线驱动器的晶体管的共同耦合的栅极，并且第二电压被提供给共同耦合的 存储器部分控制电路的存取线驱动器的晶体管的栅极耦合到非活动存储器部分控制电路，其中第一电压大于第二电压。