公开(公告)号：US20240312498A1

公开(公告)日：2024-09-19

申请号：US18674788

申请日：2024-05-24

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Mieko Kojima ,  Kazuyuki Morishige ,  Tetsuya Arai ,  Guangcan Chen

IPC: G11C7/10 ,  G11C5/06 ,  H03K19/017

CPC classification number: G11C7/1057 ,  G11C5/06 ,  G11C7/1039 ,  H03K19/01721

Abstract: Some embodiments provide an apparatus including a semiconductor substrate having source regions and regions alternately arranged in a first direction; gate electrodes between the source regions and the drain regions; a first wiring layer including first conductive patterns covering the source regions and second conductive patterns covering the drain regions; first via conductors between the first conductive patterns and the source regions; second via conductors between the second conductive patterns and the drain regions; a second wiring layer over the first wiring layer, including third conductive patterns covering the first conductive patterns and fourth conductive patterns covering the second conductive patterns; third via conductors between the third conductive patterns and the first conductive patterns; and fourth via conductors between the fourth conductive patterns and the second conductive patterns. The fourth via conductors are shifted from the third via conductors in a second direction perpendicular to the first direction.

公开(公告)号：US12020768B2

公开(公告)日：2024-06-25

申请号：US17563852

申请日：2021-12-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Mieko Kojima ,  Kazuyuki Morishige ,  Tetsuya Arai ,  Guangcan Chen

IPC: G11C7/10 ,  G11C5/06 ,  H03K19/017

CPC classification number: G11C7/1057 ,  G11C5/06 ,  G11C7/1039 ,  H03K19/01721

Abstract: Disclosed herein is an apparatus that includes a first wiring layer including first and second conductive patterns extending in a second direction and coupled to source and drain regions, respectively, and a second wiring layer including third and fourth conductive patterns extending in the second direction and coupled to the first and second conductive patterns, respectively. The first conductive pattern has first and second sections arranged in the second direction, and the second conductive pattern has third and fourth sections arranged in the second direction. The first and fourth sections are arranged in a first direction, and the second and third sections are arranged in the first direction. The third conductive pattern covers the first section without covering the second section. The fourth conductive pattern covers the third section without covering the fourth section.

公开(公告)号：US20210264967A1

公开(公告)日：2021-08-26

申请号：US16800899

申请日：2020-02-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toshiaki Tsukihashi ,  Kenichi Watanabe ,  Kazuyuki Morishige ,  Moeha Shibuya ,  Kumiko Ishii

IPC: G11C11/4093 ,  H01L27/108

Abstract: Disclosed herein is an apparatus that includes: first and second wiring patterns extending in a first direction, first and second transistors arranged adjacent to each other, and third to sixth wiring patterns extending in a second direction. The third wiring pattern is connected between the first wiring pattern and one of source/drain regions of the first transistor, the fourth wiring pattern is connected between the second wiring pattern and other of source/drain regions of the first transistor, the fifth wiring pattern is connected to one of source/drain regions of the second transistor, the fifth wiring pattern overlapping with the first wiring pattern, the sixth wiring pattern is connected to other of source/drain regions of the second transistor, the sixth wiring pattern overlapping with the second wiring pattern. The third and fourth wiring patterns are greater in width in the first direction than the fifth and sixth wiring patterns.

公开(公告)号：US10522208B1

公开(公告)日：2019-12-31

申请号：US16144693

申请日：2018-09-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kazuyuki Morishige

IPC: G11C11/4076 ,  H01L23/00 ,  G06F1/10 ,  G11C7/22

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for drivers with reduced voltage noise. Clock signals may be provided to semiconductor devices, and may be distributed throughout the device. Drivers are provided along signal paths within the device which may act as buffers for the clock signals. Each clock signal may be coupled to multiple driver circuits within the driver. Each of the multiple driver circuits may be coupled to a different pair of power supply voltage lines. The driver circuits may all have a similar delay to each other.

公开(公告)号：US11705188B2

公开(公告)日：2023-07-18

申请号：US17529101

申请日：2021-11-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toshiaki Tsukihashi ,  Kenichi Watanabe ,  Kazuyuki Morishige ,  Moeha Shibuya ,  Kumiko Ishii

IPC: G11C11/4093 ,  H10B12/00

CPC classification number: G11C11/4093 ,  H10B12/50

Abstract: Disclosed herein is an apparatus that includes: first and second wiring patterns extending in a first direction, first and second transistors arranged adjacent to each other, and third to sixth wiring patterns extending in a second direction. The third wiring pattern is connected between the first wiring pattern and one of source/drain regions of the first transistor, the fourth wiring pattern is connected between the second wiring pattern and other of source/drain regions of the first transistor, the fifth wiring pattern is connected to one of source/drain regions of the second transistor, the fifth wiring pattern overlapping with the first wiring pattern, the sixth wiring pattern is connected to other of source/drain regions of the second transistor, the sixth wiring pattern overlapping with the second wiring pattern. The third and fourth wiring patterns are greater in width in the first direction than the fifth and sixth wiring patterns.

公开(公告)号：US20220076736A1

公开(公告)日：2022-03-10

申请号：US17529101

申请日：2021-11-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toshiaki Tsukihashi ,  Kenichi Watanabe ,  Kazuyuki Morishige ,  Moeha Shibuya ,  Kumiko Ishii

IPC: G11C11/4093 ,  H01L27/108

Abstract: Disclosed herein is an apparatus that includes: first and second wiring patterns extending in a first direction, first and second transistors arranged adjacent to each other, and third to sixth wiring patterns extending in a second direction. The third wiring pattern is connected between the first wiring pattern and one of source/drain regions of the first transistor, the fourth wiring pattern is connected between the second wiring pattern and other of source/drain regions of the first transistor, the fifth wiring pattern is connected to one of source/drain regions of the second transistor, the fifth wiring pattern overlapping with the first wiring pattern, the sixth wiring pattern is connected to other of source/drain regions of the second transistor, the sixth wiring pattern overlapping with the second wiring pattern. The third and fourth wiring patterns are greater in width in the first direction than the fifth and sixth wiring patterns.

公开(公告)号：US20230206966A1

公开(公告)日：2023-06-29

申请号：US17563852

申请日：2021-12-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Mieko Kojima ,  Kazuyuki Morishige ,  Tetsuya Arai ,  Guangcan Chen

IPC: G11C7/10 ,  G11C5/06 ,  H03K19/017

CPC classification number: G11C7/1057 ,  G11C5/06 ,  G11C7/1039 ,  H03K19/01721

Abstract: Disclosed herein is an apparatus that includes a first wiring layer including first and second conductive patterns extending in a second direction and coupled to source and drain regions, respectively, and a second wiring layer including third and fourth conductive patterns extending in the second direction and coupled to the first and second conductive patterns, respectively. The first conductive pattern has first and second sections arranged in the second direction, and the second conductive pattern has third and fourth sections arranged in the second direction. The first and fourth sections are arranged in a first direction, and the second and third sections are arranged in the first direction. The third conductive pattern covers the first section without covering the second section. The fourth conductive pattern covers the third section without covering the fourth section.

公开(公告)号：US11183232B2

公开(公告)日：2021-11-23

申请号：US16800899

申请日：2020-02-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toshiaki Tsukihashi ,  Kenichi Watanabe ,  Kazuyuki Morishige ,  Moeha Shibuya ,  Kumiko Ishii

IPC: G06F1/16 ,  G11C11/4093 ,  H01L27/108

Abstract: Disclosed herein is an apparatus that includes: first and second wiring patterns extending in a first direction, first and second transistors arranged adjacent to each other, and third to sixth wiring patterns extending in a second direction. The third wiring pattern is connected between the first wiring pattern and one of source/drain regions of the first transistor, the fourth wiring pattern is connected between the second wiring pattern and other of source/drain regions of the first transistor, the fifth wiring pattern is connected to one of source/drain regions of the second transistor, the fifth wiring pattern overlapping with the first wiring pattern, the sixth wiring pattern is connected to other of source/drain regions of the second transistor, the sixth wiring pattern overlapping with the second wiring pattern. The third and fourth wiring patterns are greater in width in the first direction than the fifth and sixth wiring patterns.

公开(公告)号：US10896720B2

公开(公告)日：2021-01-19

申请号：US16692204

申请日：2019-11-22

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kazuyuki Morishige

IPC: G11C11/40 ,  G11C11/4076 ,  H01L23/00 ,  G06F1/10 ,  G11C7/22

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for drivers with reduced voltage noise. Clock signals may be provided to semiconductor devices, and may be distributed throughout the device. Driven are provided along signal paths within the device which may act as buffers for the clock signals. Each clock signal may be coupled to multiple driver circuits within the driver. Each of the multiple driver circuits may be coupled to a different pair of power supply voltage lines. The driver circuits may all have a similar delay to each other.