公开(公告)号：US12191162B2

公开(公告)日：2025-01-07

申请号：US17189006

申请日：2021-03-01

Applicant: Micron Technology, Inc.

Inventor： Owen R. Fay ,  Akshay N. Singh ,  Kyle K. Kirby

IPC: H01L21/48 ,  H01L21/66 ,  H01L23/48 ,  H01L23/498 ,  H01L25/065 ,  H01L23/00

Abstract: A semiconductor device assembly and method of forming a semiconductor device assembly that includes a first substrate, a second substrate disposed over the first substrate, at least one interconnect between the substrates, and at least one pillar extending from the bottom surface of the first substrate. The pillar is electrically connected to the interconnect and is located adjacent to a side of the first substrate. The pillar is formed by filling a via through the substrate with a conductive material. The first substrate may include an array of pillars extending from the bottom surface adjacent to a side of the substrate that are formed from a plurality of filled vias. The substrate may include a test pad located on the bottom surface or located on the top surface. The pillars may include a removable coating enabling the pillars to be probed without damaging the inner conductive portion of the pillar.

公开(公告)号：US20240379503A1

公开(公告)日：2024-11-14

申请号：US18780303

申请日：2024-07-22

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Kyle K. Kirby ,  Bret K. Street ,  Kunal R. Parekh

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L25/065

Abstract: A semiconductor device having monolithic conductive columns, and associated systems and methods, are disclosed herein. The semiconductor device can include a semiconductor substrate, a conductive pad, an opening, a non-conductive liner, and a plug of non-conductive material. The conductive pad may be at a surface of the semiconductor substrate. The opening may extend through the semiconductor substrate from the conductive pad to a second surface and define a side wall. The liner may coat the side wall and the plug may fill the opening. A second opening may be formed through the semiconductor device and the opening and a conductive material plated therein.

公开(公告)号：US20240222300A1

公开(公告)日：2024-07-04

申请号：US18610263

申请日：2024-03-20

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby

IPC: H01L23/00 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L24/08 ,  H01L24/05 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05557 ,  H01L2224/08146 ,  H01L2224/80143

Abstract: Semiconductor devices having interconnect structures with vertically offset bonding surfaces, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a semiconductor substrate at least partially covered by a first dielectric material having an upper surface, and an interconnect structure extending therefrom. The interconnect structure can include a plurality of conductive elements, and a continuous region of a first insulating material at least partially between the plurality of conductive elements. The plurality of conductive elements and the continuous region can have coplanar end surfaces. The interconnect structure can further include a perimeter structure at least partially surrounding the plurality of conductive elements and the continuous region. The perimeter structure can have an uppermost surface that can be vertically offset from the upper surface of the first dielectric material and/or the coplanar end surfaces.

公开(公告)号：US20240071968A1

公开(公告)日：2024-02-29

申请号：US18199741

申请日：2023-05-19

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby ,  Terrence B. McDaniel ,  Wei Zhou

IPC: H01L23/00

CPC classification number: H01L24/08 ,  H01L24/05 ,  H01L24/80 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/0807 ,  H01L2224/08123 ,  H01L2224/08145 ,  H01L2224/80365 ,  H01L2224/80379 ,  H01L2224/80896 ,  H01L2924/04642 ,  H01L2924/0504 ,  H01L2924/0554 ,  H01L2924/059

Abstract: This document discloses techniques, apparatuses, and systems for semiconductor device interconnects formed through volumetric expansion. A semiconductor assembly is described that includes two semiconductor dies. The first semiconductor die and the second semiconductor die are bonded at a dielectric layer of the first semiconductor die and a dielectric layer of the second semiconductor die to create one or more interconnect openings. The first semiconductor die includes a reservoir of conductive material located adjacent to the one or more interconnect openings and having a width greater than a width of the one or more interconnect openings. The reservoir of conductive material is heated to volumetrically expand the reservoir of conductive material through the one or more interconnect openings to form one or more interconnects electrically coupling the first semiconductor die and the second semiconductor die. In this way, a connected semiconductor device may be assembled.

公开(公告)号：US20230260877A1

公开(公告)日：2023-08-17

申请号：US17670393

申请日：2022-02-11

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Kyle K. Kirby ,  Bret K. Street ,  Kunal R. Parekh

IPC: H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L24/16 ,  H01L25/0657 ,  H01L21/76898 ,  H01L2225/06541

Abstract: A semiconductor device having monolithic conductive cylinders, and associated systems and methods, are disclosed herein. The semiconductor device can include a semiconductor substrate, a conductive pad, an opening, and a top dielectric layer. The conductive pad may be at a first surface of the semiconductor substrate. The opening may be ring-shaped and extend through the semiconductor substrate from the conductive pad to a second surface and define a side wall. The liner may coat the side wall and the top dielectric layer may cover the second surface and may fill the opening. A second ring-shaped opening may be formed through the semiconductor device and the opening and a conductive material plated therein.

公开(公告)号：US20230060594A1

公开(公告)日：2023-03-02

申请号：US17858001

申请日：2022-07-05

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby

IPC: H01L23/00 ,  H01L25/065

Abstract: A semiconductor device includes a semiconductor substrate having a first major surface and a second major surface opposite the first major surface, a first layer of dielectric material over the first major surface, and a second layer of dielectric material over the second major surface. The first layer includes a plurality of recesses, and the second layer includes a plurality of protrusions. Each of the plurality of recesses are defined by a shape, and each of the plurality of protrusions are vertically aligned with a corresponding one of the plurality of recesses and are defined by the shape of the corresponding one of the plurality of recesses.

公开(公告)号：US11532578B2

公开(公告)日：2022-12-20

申请号：US17201874

申请日：2021-03-15

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00

Abstract: A substrate or semiconductor device, semiconductor device assembly, and method of forming a semiconductor device assembly that includes a barrier on a solder cup. The semiconductor device assembly includes a substrate disposed over another substrate. At least one solder cup extends from one substrate towards an under bump metal (UBM) on the other substrate. The barrier on the exterior of the solder cup may be a standoff to control a bond line between the substrates. The barrier may reduce solder bridging during the formation of a semiconductor device assembly. The barrier may help to align the solder cup with a UBM when forming a semiconductor device assembly and may reduce misalignment due to lateral movement of substrates and/or semiconductor devices.

公开(公告)号：US20220102308A1

公开(公告)日：2022-03-31

申请号：US17035579

申请日：2020-09-28

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby ,  Bret K. Street

IPC: H01L23/00 ,  H01L23/48 ,  H01L25/065 ,  H01L25/00

Abstract: Systems and methods for semiconductor devices having a substrate with bond pads, a die pair in a stacked configuration above the bond pads and having a first die having an oxide layer, a second die having an oxide layer attached to the first oxide layer, and conductive bonds electrically coupling the dies. Interconnects extend between the bond pads and the die pair, electrically coupling die pair to the substrate. The device may include a second die pair electrically coupled to: (1) the first die pair with secondary interconnects; and (2) the substrate with through-silicon vias extending through the first die pair. The top die of a die pair may be a thick die for use at the top of a pair stack. Pairs may be created by matching dies of a first silicon wafer to dies of a second silicon wafer, combination bonding the wafers, and dicing the die pairs.

公开(公告)号：US20220068819A1

公开(公告)日：2022-03-03

申请号：US17325069

申请日：2021-05-19

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby ,  Kunal R. Parekh

IPC: H01L23/538 ,  H01L27/06 ,  H01L27/092 ,  H01L21/50 ,  H01L21/768

Abstract: Systems and methods for a semiconductor device having a front-end-of-line interconnect structure are provided. The semiconductor device may include a dielectric material having a backside formed on a front side of a semiconductor or silicon substrate material and a front side, and a conducting material on the front side of the dielectric material. The conducting material may have a line portion and an interconnect structure electrically coupled to the line portion and separated from the front side of the substrate material by the dielectric material. The interconnect structure has a backside defining a contact surface. The semiconductor device may further include a semiconductor die proximate the front side of the dielectric material, an insulating material encasing at least a portion of the semiconductor die, and an opening through which the active contact surface at the backside of the interconnect structure is exposed for electrical connection.

公开(公告)号：US10796989B2

公开(公告)日：2020-10-06

申请号：US16138838

申请日：2018-09-21

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby

IPC: H01L23/522 ,  H01L23/48 ,  H01L25/065

Abstract: A semiconductor device having a first die and a second die is provided. The first die of the device includes a first surface and a through-substrate via (TSV) extending at least substantially through the first die, the TSV having a portion extending past the first surface. The first die further includes a first substantially helical conductor disposed around the TSV. The second die of the device includes a second surface, an opening in the second surface in which the portion of the TSV is disposed, and a second substantially helical conductor disposed around the opening.