公开(公告)号：US12119315B2

公开(公告)日：2024-10-15

申请号：US17650851

申请日：2022-02-13

申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

发明人： Chih-Wei Chang

IPC分类号： H01L21/768 ,  H01L23/00 ,  H01L23/48 ,  H01L25/065

CPC分类号： H01L24/05 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/03 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L2224/03622 ,  H01L2224/05009 ,  H01L2224/05011 ,  H01L2224/05014 ,  H01L2224/05015 ,  H01L2224/05017 ,  H01L2224/05073 ,  H01L2224/0801 ,  H01L2224/08055 ,  H01L2224/08056 ,  H01L2224/08059 ,  H01L2224/0807 ,  H01L2224/08147 ,  H01L2224/08148 ,  H01L2224/80895 ,  H01L2225/06524 ,  H01L2225/06544 ,  H01L2225/06548

摘要： A chip bonding method includes the following operations. A first chip is provided, which includes a first contact pad including a first portion lower than a first surface of a first substrate and a second portion higher than the first surface of the first substrate to form the stepped first contact pad. A second chip is provided, which includes a second contact pad including a third portion lower than a third surface of a second substrate and a fourth portion higher than the third surface of the second substrate to form the stepped second contact pad. The first chip and the second chip are bonded. The first portion of the first chip contacts with the fourth portion of the second chip, and the second portion of the first chip contacts with the third portion of the second chip.

公开(公告)号：US20240282713A1

公开(公告)日：2024-08-22

申请号：US18173027

申请日：2023-02-22

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chen-Hsuan Tsai ,  Yu-Lin CHIANG ,  Chin-Chuan Chang ,  Ying-Ching Shih

IPC分类号： H01L23/538 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/10

CPC分类号： H01L23/5386 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5381 ,  H01L23/5385 ,  H01L24/05 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L25/105 ,  H01L2224/05687 ,  H01L2224/0569 ,  H01L2224/0801 ,  H01L2224/08058 ,  H01L2224/08059 ,  H01L2224/0807 ,  H01L2224/08235 ,  H01L2224/08238 ,  H01L2224/16235 ,  H01L2224/3201 ,  H01L2224/32059 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/80203 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/81203 ,  H01L2224/83203 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/107 ,  H01L2924/1811 ,  H01L2924/1815 ,  H01L2924/182 ,  H01L2924/186

摘要： A package structure includes a first redistribution circuit structure, a first semiconductor die, and a second semiconductor die. The first redistribution circuit structure has a first side and a second side opposite to the first side. The first semiconductor die is disposed over the firs side of the first redistribution circuit structure. The second semiconductor die is disposed over the second side of the first redistribution circuit structure and is electrically connected thereto, where the second semiconductor die includes a substrate, an interconnect structure disposed on the substrate, a plurality of conductive terminals disposed on and electrically connected to the interconnect structure, and a dielectric layer disposed on the interconnect structure and laterally covering the plurality of conductive terminals. A material of the dielectric layer included in the second semiconductor die is different from a material of a dielectric layer included in the first redistribution circuit structure.

公开(公告)号：US20230378110A1

公开(公告)日：2023-11-23

申请号：US18067773

申请日：2022-12-19

申请人： Samsung Electronics Co., Ltd.

发明人： MINKI KIM ,  Seungduk Baek ,  Hyuekjae Lee

IPC分类号： H01L23/00 ,  H10B80/00

CPC分类号： H01L24/08 ,  H10B80/00 ,  H01L24/03 ,  H01L24/05 ,  H01L24/80 ,  H01L2924/1438 ,  H01L2924/1431 ,  H01L2224/0801 ,  H01L2224/08056 ,  H01L2224/08055 ,  H01L2224/0807 ,  H01L2224/08059 ,  H01L2224/08058 ,  H01L2224/08121 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2224/05647 ,  H01L2224/05687 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/03831 ,  H01L2224/0384

摘要： Provided is a semiconductor device including lower and upper structures. The lower structure includes a first substrate, a first pad on the first substrate, and a first insulating layer surrounding the first pad. The upper structure includes a second substrate, a second pad on the second substrate, and a second insulating layer surrounding the second pad. The upper and lower structures contact each other. The first and second pads contact each other. The first and second insulating layers contact each other. The first insulating layer includes a first recess adjacent the first pad, the second insulating layer includes a second recess that is adjacent the second pad and overlaps the first recess, and a cavity is defined by the first recess and the second recess, and particles of a metallic material constituting the first and second pads are in the cavity.

公开(公告)号：US20190244899A1

公开(公告)日：2019-08-08

申请号：US16388692

申请日：2019-04-18

申请人： Invensas Bonding Technologies, Inc.

发明人： Paul M. Enquist ,  Gaius Gillman Fountain, JR. ,  Javier A. DeLaCruz

IPC分类号： H01L23/528 ,  H01L23/522 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L21/768

CPC分类号： H01L23/5283 ,  H01L21/76838 ,  H01L23/5226 ,  H01L24/02 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05541 ,  H01L2224/05551 ,  H01L2224/05552 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05578 ,  H01L2224/056 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05684 ,  H01L2224/0807 ,  H01L2224/08111 ,  H01L2224/08121 ,  H01L2224/08146 ,  H01L2224/08147 ,  H01L2224/08148 ,  H01L2224/08237 ,  H01L2224/08238 ,  H01L2224/16145 ,  H01L2224/80 ,  H01L2224/80035 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80935 ,  H01L2225/06513 ,  H01L2225/06555 ,  H01L2225/06593 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2924/206 ,  H01L2924/00012

摘要： A bonded device structure including a first substrate having a first set of conductive contact structures, preferably connected to a device or circuit, and having a first non-metallic region adjacent to the contact structures on the first substrate, a second substrate having a second set of conductive contact structures, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the contact structures on the second substrate, and a contact-bonded interface between the first and second set of contact structures formed by contact bonding of the first non-metallic region to the second non-metallic region. The contact structures include elongated contact features, such as individual lines or lines connected in a grid, that are non-parallel on the two substrates, making contact at intersections. Alignment tolerances are thus improved while minimizing dishing and parasitic capacitance.

公开(公告)号：US20180114763A1

公开(公告)日：2018-04-26

申请号：US15851186

申请日：2017-12-21

申请人： NANYA TECHNOLOGY CORPORATION

发明人： PO CHUN LIN

IPC分类号： H01L23/00

CPC分类号： H01L24/05 ,  H01L24/02 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0231 ,  H01L2224/02311 ,  H01L2224/02321 ,  H01L2224/0233 ,  H01L2224/02351 ,  H01L2224/0239 ,  H01L2224/0383 ,  H01L2224/03831 ,  H01L2224/039 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05557 ,  H01L2224/05567 ,  H01L2224/0807 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/13022 ,  H01L2224/94 ,  H01L2924/00012 ,  H01L2224/03 ,  H01L2224/11

摘要： The present disclosure provides a method for manufacturing a semiconductor structure. The semiconductor structure includes a substrate having a first surface and a second surface opposite to the first surface; a pad disposed over the first surface; a first passivation disposed over the first surface and partially covering the pad; a redistribution layer (RDL) disposed over the first passivation, and including a conductive line extending over the first passivation and a second passivation partially covering the conductive line. The conductive line includes a via portion coupled with the pad and extended within the first passivation towards the pad, and a land portion extended over the first passivation, wherein the land portion includes a plurality of first protrusions protruded away from the first passivation.

公开(公告)号：US20150287692A1

公开(公告)日：2015-10-08

申请号：US14746425

申请日：2015-06-22

申请人： ZIPTRONIX, INC.

发明人： Paul M. ENQUIST ,  Gaius Gillman FOUNTAIN, JR.

IPC分类号： H01L23/00 ,  H01L27/06

CPC分类号： H01L24/08 ,  H01L21/187 ,  H01L21/2007 ,  H01L21/6835 ,  H01L21/76251 ,  H01L21/76898 ,  H01L21/8221 ,  H01L23/13 ,  H01L23/36 ,  H01L23/481 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/24 ,  H01L24/26 ,  H01L24/27 ,  H01L24/30 ,  H01L24/48 ,  H01L24/80 ,  H01L24/82 ,  H01L24/83 ,  H01L24/94 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/167 ,  H01L25/18 ,  H01L25/50 ,  H01L27/0688 ,  H01L27/14634 ,  H01L2221/6835 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2223/6677 ,  H01L2224/0807 ,  H01L2224/08123 ,  H01L2224/1134 ,  H01L2224/16 ,  H01L2224/24011 ,  H01L2224/24225 ,  H01L2224/24226 ,  H01L2224/24227 ,  H01L2224/3005 ,  H01L2224/30104 ,  H01L2224/305 ,  H01L2224/48091 ,  H01L2224/48101 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/80896 ,  H01L2224/81894 ,  H01L2224/8303 ,  H01L2224/83092 ,  H01L2224/83099 ,  H01L2224/8319 ,  H01L2224/83193 ,  H01L2224/83345 ,  H01L2224/83359 ,  H01L2224/8385 ,  H01L2224/83894 ,  H01L2224/83896 ,  H01L2224/83912 ,  H01L2224/83948 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06589 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/05442 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13063 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/351 ,  Y10S148/012 ,  Y10S438/977 ,  H01L2224/13099 ,  H01L2924/01049 ,  H01L2924/01031 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/8203 ,  H01L2224/821 ,  H01L2224/80001 ,  H01L2224/82

摘要： A device integration method and integrated device. The method may include the steps of directly bonding a semiconductor device having a substrate to an element; and removing a portion of the substrate to expose a remaining portion of the semiconductor device after bonding. The element may include one of a substrate used for thermal spreading, impedance matching or for RF isolation, an antenna, and a matching network comprised of passive elements. A second thermal spreading substrate may be bonded to the remaining portion of the semiconductor device. Interconnections may be made through the first or second substrates. The method may also include bonding a plurality of semiconductor devices to an element, and the element may have recesses in which the semiconductor devices are disposed. A conductor array having a plurality of contact structures may be formed on an exposed surface of the semiconductor device, vias may be formed through the semiconductor device to device regions, and interconnection may be formed between said device regions and said contact structures.

摘要翻译： 一种器件集成方法和集成器件。 该方法可以包括将具有衬底的半导体器件直接接合到元件的步骤; 以及去除所述衬底的一部分以在结合之后露出所述半导体器件的剩余部分。 元件可以包括用于热扩散，阻抗匹配或RF隔离的衬底之一，天线以及由无源元件组成的匹配网络。 第二热扩散基板可以结合到半导体器件的其余部分。 互连可以通过第一或第二基底进行。 该方法还可以包括将多个半导体器件接合到元件，并且元件可以具有设置半导体器件的凹部。 具有多个接触结构的导体阵列可以形成在半导体器件的暴露表面上，可以通过半导体器件到器件区域形成通孔，并且可以在所述器件区域和所述接触结构之间形成互连。

公开(公告)号：US20080093747A1

公开(公告)日：2008-04-24

申请号：US11980665

申请日：2007-10-31

申请人： Paul Enquist ,  Gaius Fountain

发明人： Paul Enquist ,  Gaius Fountain

IPC分类号： H01L23/52 ,  H01L21/98

CPC分类号： H01L24/08 ,  H01L21/187 ,  H01L21/2007 ,  H01L21/6835 ,  H01L21/76251 ,  H01L21/76898 ,  H01L21/8221 ,  H01L23/13 ,  H01L23/36 ,  H01L23/481 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/24 ,  H01L24/26 ,  H01L24/27 ,  H01L24/30 ,  H01L24/48 ,  H01L24/80 ,  H01L24/82 ,  H01L24/83 ,  H01L24/94 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/167 ,  H01L25/18 ,  H01L25/50 ,  H01L27/0688 ,  H01L27/14634 ,  H01L2221/6835 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2223/6677 ,  H01L2224/0807 ,  H01L2224/08123 ,  H01L2224/1134 ,  H01L2224/16 ,  H01L2224/24011 ,  H01L2224/24225 ,  H01L2224/24226 ,  H01L2224/24227 ,  H01L2224/3005 ,  H01L2224/30104 ,  H01L2224/305 ,  H01L2224/48091 ,  H01L2224/48101 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/80896 ,  H01L2224/81894 ,  H01L2224/8303 ,  H01L2224/83092 ,  H01L2224/83099 ,  H01L2224/8319 ,  H01L2224/83193 ,  H01L2224/83345 ,  H01L2224/83359 ,  H01L2224/8385 ,  H01L2224/83894 ,  H01L2224/83896 ,  H01L2224/83912 ,  H01L2224/83948 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06589 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/05442 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13063 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/351 ,  Y10S148/012 ,  Y10S438/977 ,  H01L2224/13099 ,  H01L2924/01049 ,  H01L2924/01031 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/8203 ,  H01L2224/821 ,  H01L2224/80001 ,  H01L2224/82

摘要： A device integration method and integrated device. The method may include the steps of directly bonding a semiconductor device having a substrate to an element; and removing a portion of the substrate to expose a remaining portion of the semiconductor device after bonding. The element may include one of a substrate used for thermal spreading, impedance matching or for RF isolation, an antenna, and a matching network comprised of passive elements. A second thermal spreading substrate may be bonded to the remaining portion of the semiconductor device. Interconnections may be made through the first or second substrates. The method may also include bonding a plurality of semiconductor devices to an element, and the element may have recesses in which the semiconductor devices are disposed. A conductor array having a plurality of contact structures may be formed on an exposed surface of the semiconductor device, vias may be formed through the semiconductor device to device regions, and interconnection may be formed between said device regions and said contact structures.

公开(公告)号：US20230361066A1

公开(公告)日：2023-11-09

申请号：US17662493

申请日：2022-05-09

申请人： SANDISK TECHNOLOGIES LLC

发明人： Linghan CHEN ,  Lin HOU

IPC分类号： H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

CPC分类号： H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H01L24/05 ,  H01L24/03 ,  H01L24/80 ,  H01L25/50 ,  H01L2224/05082 ,  H01L2224/05147 ,  H01L2224/05157 ,  H01L2224/05166 ,  H01L2224/05176 ,  H01L2224/05181 ,  H01L2224/0807 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/14511 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2224/03616

摘要： Bonding strength and yield can be enhanced by providing a mating pair of a convex bonding surface and a concave bonding surface. The convex bonding surface can be provided by employing a conductive barrier layer having a higher electrochemical potential than copper. The concave bonding surface can be provided by employing a conductive barrier layer having a lower electrochemical potential than copper. Alternatively additionally, a copper material portion in a bonding pad may include at least 10% volume fraction of (200) copper grains to provide high volume expansion toward a mating copper material portion. The mating copper material portion may be formed with at least 95% volume fraction of (111) copper grains to provide high surface diffusivity, or may be formed with at least 10% volume fraction of (200) copper grains to provide high volume expansion.

公开(公告)号：US09786583B2

公开(公告)日：2017-10-10

申请号：US15169623

申请日：2016-05-31

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Yan Xun Xue ,  Hamza Yilmaz ,  Yueh-Se Ho ,  Jun Lu ,  De Mei Gong

IPC分类号： H01L21/00 ,  H01L23/495 ,  H01L21/78 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00

CPC分类号： H01L23/49562 ,  H01L21/4825 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49568 ,  H01L23/49811 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/0603 ,  H01L2224/0807 ,  H01L2224/16 ,  H01L2224/16245 ,  H01L2224/29139 ,  H01L2224/29294 ,  H01L2224/293 ,  H01L2224/3207 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49176 ,  H01L2224/49177 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/80345 ,  H01L2224/80357 ,  H01L2224/80897 ,  H01L2224/81 ,  H01L2224/83801 ,  H01L2224/83805 ,  H01L2224/92242 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/18301 ,  H01L2224/85 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2924/014 ,  H01L2224/83 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

摘要： A power semiconductor package device and a method of preparation the device are disclosed. The package device includes a die paddle, a first pin, a second pin, and a semiconductor chip attached to the die paddle. A first electrode, a second electrode and a third electrode of the semiconductor chip are connected to the first pin, the second pin and the die paddle respectively. A plastic package body covers the semiconductor chip, the die paddle, the first pin and the second pin. The first pin and the second pin are located near two adjacent corners of the plastic package body. The bottom surface and two side surfaces of each of the first pin and the second pin are exposed from the plastic package body. Locking mechanisms are constructed to prevent the first pin and the second pin from falling off the power semiconductor package device during a manufacturing cutting process. Portions of the first pin, portions of the second pin, and portions of the plastic package body can be cut off. Therefore, the size of the power semiconductor package device is reduced.

公开(公告)号：US09431368B2

公开(公告)日：2016-08-30

申请号：US15064467

申请日：2016-03-08

申请人： ZIPTRONIX, INC.

发明人： Paul M. Enquist ,  Gaius Gillman Fountain, Jr.

IPC分类号： H01L21/58 ,  H01L23/00 ,  H01L21/20 ,  H01L21/683 ,  H01L21/768 ,  H01L21/822 ,  H01L23/13 ,  H01L23/36 ,  H01L23/48 ,  H01L23/538 ,  H01L25/065 ,  H01L25/16 ,  H01L25/00 ,  H01L27/06 ,  H01L21/762 ,  H01L23/552 ,  H01L25/18 ,  H01L27/146

CPC分类号： H01L24/08 ,  H01L21/187 ,  H01L21/2007 ,  H01L21/6835 ,  H01L21/76251 ,  H01L21/76898 ,  H01L21/8221 ,  H01L23/13 ,  H01L23/36 ,  H01L23/481 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/24 ,  H01L24/26 ,  H01L24/27 ,  H01L24/30 ,  H01L24/48 ,  H01L24/80 ,  H01L24/82 ,  H01L24/83 ,  H01L24/94 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/167 ,  H01L25/18 ,  H01L25/50 ,  H01L27/0688 ,  H01L27/14634 ,  H01L2221/6835 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2223/6677 ,  H01L2224/0807 ,  H01L2224/08123 ,  H01L2224/1134 ,  H01L2224/16 ,  H01L2224/24011 ,  H01L2224/24225 ,  H01L2224/24226 ,  H01L2224/24227 ,  H01L2224/3005 ,  H01L2224/30104 ,  H01L2224/305 ,  H01L2224/48091 ,  H01L2224/48101 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/80896 ,  H01L2224/81894 ,  H01L2224/8303 ,  H01L2224/83092 ,  H01L2224/83099 ,  H01L2224/8319 ,  H01L2224/83193 ,  H01L2224/83345 ,  H01L2224/83359 ,  H01L2224/8385 ,  H01L2224/83894 ,  H01L2224/83896 ,  H01L2224/83912 ,  H01L2224/83948 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06589 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/05442 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13063 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/351 ,  Y10S148/012 ,  Y10S438/977 ,  H01L2224/13099 ,  H01L2924/01049 ,  H01L2924/01031 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/8203 ,  H01L2224/821 ,  H01L2224/80001 ,  H01L2224/82

摘要： A method may include the steps of directly bonding a semiconductor device having a substrate to an element; and removing a portion of the substrate to expose a remaining portion of the semiconductor device after bonding. The element may include one of a substrate used for thermal spreading, impedance matching or for RF isolation, an antenna, and a matching network comprised of passive elements. A second thermal spreading substrate may be bonded to the remaining portion of the semiconductor device. Interconnections may be made through the first or second substrates. The method may also include bonding a plurality of semiconductor devices to an element, and the element may have recesses in which the semiconductor devices are disposed.

摘要翻译： 一种方法可以包括将具有衬底的半导体器件直接接合到元件的步骤; 以及去除所述衬底的一部分以在结合之后露出所述半导体器件的剩余部分。 元件可以包括用于热扩散，阻抗匹配或RF隔离的衬底之一，天线以及由无源元件组成的匹配网络。 第二热扩散基板可以结合到半导体器件的其余部分。 互连可以通过第一或第二基底进行。 该方法还可以包括将多个半导体器件接合到元件，并且元件可以具有设置半导体器件的凹部。