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    DUAL DATA CHANNEL PEAK POWER MANAGEMENT
    1.
    发明公开
    DUAL DATA CHANNEL PEAK POWER MANAGEMENT 审中-公开

    公开(公告)号：US20240143501A1

    公开(公告)日：2024-05-02

    申请号：US18494841

    申请日：2023-10-26

    Applicant: Micron Technology, Inc.

    Inventor： Luca Nubile ,  Luigi Pilolli ,  Liang Yu ,  Ali Mohammadzadeh ,  Walter Di Francesco ,  Biagio Iorio

    IPC: G06F12/02 ,  G06F1/28

    CPC classification number: G06F12/0246 ,  G06F1/28

    Abstract: A memory device includes a plurality of memory dies. Each memory die of the plurality of memory dies includes a memory die and control logic, operatively coupled with the memory die, to perform operations including receiving, during a current auxiliary data communication cycle, a token to enable auxiliary data communication, in response to receiving the token, determining whether to communicate auxiliary data via an auxiliary data channel to at least one other memory die of a plurality of memory dies, and in response to determining to communicate the auxiliary data via the auxiliary data channel to the at least one other memory die, causing the auxiliary data to be communicated to the at least one other memory die.

    PEAK POWER MANAGEMENT WITH DATA WINDOW RESERVATION
    5.
    发明公开
    PEAK POWER MANAGEMENT WITH DATA WINDOW RESERVATION 审中-公开

    公开(公告)号：US20230305616A1

    公开(公告)日：2023-09-28

    申请号：US18123399

    申请日：2023-03-20

    Applicant: Micron Technology, Inc.

    Inventor： Luca Nubile ,  Walter Di Francesco ,  Luigi Pilolli

    IPC: G06F1/3225 ,  G06F1/10

    CPC classification number: G06F1/3225 ,  G06F1/10

    Abstract: A memory device includes memory dies, a first memory die of the memory dies including a memory array and control logic, operatively coupled with the memory array, to perform peak power management (PPM) operations including receiving a token from another memory die, in response to receiving the token, determining whether to reserve a data window during a token circulation time period having a first size determined based on a common clock signal shared among the memory dies and, in response to determining to reserve the data window, causing the data window to be reserved. The data window has a second size different from the first size determined based on the common clock signal. The operations further include causing a data frame to be generated within the data window. The data frame has a third size determined from the second size and includes current consumption information for the memory device.

    CHECKING STATUS OF MULTIPLE MEMORY DIES IN A MEMORY SUB-SYSTEM
    6.
    发明申请
    CHECKING STATUS OF MULTIPLE MEMORY DIES IN A MEMORY SUB-SYSTEM 有权

    公开(公告)号：US20220011970A1

    公开(公告)日：2022-01-13

    申请号：US16946871

    申请日：2020-07-09

    Applicant: Micron Technology, Inc.

    Inventor： Luca Nubile ,  Luca De Santis

    IPC: G06F3/06

    Abstract: A processing device in a memory sub-system assigns each of a plurality of memory units associated with one or more memory die of a memory device a unique address by which each of the plurality of memory units is identified. The processing device further sends a multi-unit status command to the memory device, the multi-unit status command specifying a subset of the plurality of memory units using corresponding unique addresses and receives a response to the multi-unit status command, the response comprising a multi-bit value comprising a plurality of bits, wherein each bit of the plurality of bits represents a status of one or more parameters of a plurality of parameters for a corresponding one of the plurality of memory units.

    Prioritized power budget arbitration for multiple concurrent memory access operations
    7.
    发明授权
    Prioritized power budget arbitration for multiple concurrent memory access operations 有权

    公开(公告)号：US12282669B2

    公开(公告)日：2025-04-22

    申请号：US18621747

    申请日：2024-03-29

    Applicant: Micron Technology, Inc.

    Inventor： Luca Nubile ,  Walter Di Francesco ,  Fumin Gu ,  Ali Mohammadzadeh ,  Biagio Iorio ,  Liang Yu

    IPC: G06F3/06

    Abstract: A memory device includes a memory array and control logic, operatively coupled with the memory array. The control logic allocates power to one or more prioritized processing threads, of a plurality of processing threads that access the memory array, based on a value of a priority ring counter. The control logic starts a timer in response to detecting allocation of the power to a non-prioritized processing thread of the plurality of processing threads. While the timer is running, the control logic increments the priority ring counter before each power management cycle and prioritizes allocation of the power to the one or more prioritized processing threads located within a subset of the plurality of processing threads corresponding to a value of the priority ring counter.

    Checking status of multiple memory dies in a memory sub-system
    10.
    发明授权
    Checking status of multiple memory dies in a memory sub-system 有权

    公开(公告)号：US11681467B2

    公开(公告)日：2023-06-20

    申请号：US16946871

    申请日：2020-07-09

    Applicant: Micron Technology, Inc.

    Inventor： Luca Nubile ,  Luca De Santis

    IPC: G06F3/06

    CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0673

    Abstract: A processing device in a memory sub-system assigns each of a plurality of memory units associated with one or more memory die of a memory device a unique address by which each of the plurality of memory units is identified. The processing device further sends a multi-unit status command to the memory device, the multi-unit status command specifying a subset of the plurality of memory units using corresponding unique addresses and receives a response to the multi-unit status command, the response comprising a multi-bit value comprising a plurality of bits, wherein each bit of the plurality of bits represents a status of one or more parameters of a plurality of parameters for a corresponding one of the plurality of memory units.

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