公开(公告)号：US20240428842A1

公开(公告)日：2024-12-26

申请号：US18743309

申请日：2024-06-14

Applicant: Micron Technology, Inc.

Inventor： Yang Lu ,  Randall J. Rooney ,  David R. Brown ,  Michael A. Shore ,  Kang-Yong Kim

IPC: G11C11/406 ,  G11C11/4076

Abstract: Apparatuses, systems, and methods for multiple types of alert along an alert bus. A memory device may detect multiple types of alert and use an alert signal along an alert bus to signal a controller of these alerts. Different pulse widths of the alert signal may be used to indicate the type of alert. For example if the alert signal is at an active level between a first duration and a second duration, it may indicate a first type of alert, if the alert signal is active between a third duration and a fourth duration, it may indicate a second type of alert. If the alert signal remains active for longer than a threshold amount of time, it may indicate a third type of alert.

公开(公告)号：US11972788B2

公开(公告)日：2024-04-30

申请号：US17301970

申请日：2021-04-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Nathaniel J. Meier ,  Michael A. Shore

IPC: G11C11/406 ,  G11C11/4076 ,  G11C11/408

CPC classification number: G11C11/40622 ,  G11C11/40615 ,  G11C11/4076 ,  G11C11/4085 ,  G11C11/4087

Abstract: Apparatuses, systems, and methods for controller directed targeted refresh operations. A memory may be coupled to a controller. The memory may identify aggressor addresses based on sampled addresses. The addresses may be sampled based on internal timing logic of the memory and also based on a sampling command received from the controller. The memory may also receive a controller identified aggressor address from the controller. The memory may refresh one or more victim word lines of the identified (either by the memory or the controller) aggressor addresses as part of a targeted refresh operation. Victims of controller identified aggressor addresses may be refreshed before memory identified aggressor addresses.

公开(公告)号：US11901005B2

公开(公告)日：2024-02-13

申请号：US16953092

申请日：2020-11-19

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Michael A. Shore

IPC: G11C11/00 ,  G11C14/00 ,  G11C11/22 ,  G11C11/4091 ,  G11C11/4097 ,  H01L49/02 ,  G11C11/4096 ,  H01L27/105 ,  H10B12/00 ,  H10B53/30 ,  H10B53/40

CPC classification number: G11C14/0027 ,  G11C11/005 ,  G11C11/221 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/4097 ,  H01L27/105 ,  H01L28/40 ,  H01L28/55 ,  H10B12/00 ,  H10B12/09 ,  H10B12/30 ,  H10B53/30 ,  H10B53/40

Abstract: Apparatuses and methods for memory including ferroelectric memory cells and dielectric memory cells are disclosed. The apparatus includes a first memory cell including first and second ferroelectric capacitors configured to store charges representing complementary logical values, a second memory cell including first and second dielectric capacitors configured to store charges representing complementary logical values, a first bit line selectably coupled to the first ferroelectric capacitor of the first memory cell and to the first dielectric capacitor of the second memory cell, a second bit line selectably coupled to the second ferroelectric capacitor of the first memory cell and to the second dielectric capacitor of the second memory cell, and a sense amplifier coupled to the first and second bit lines.

公开(公告)号：US20240038290A1

公开(公告)日：2024-02-01

申请号：US17877296

申请日：2022-07-29

Applicant: Micron Technology, Inc.

Inventor： Michael A. Shore ,  Nathaniel J. Meier

IPC: G11C11/4078 ,  G11C11/406

CPC classification number: G11C11/4078 ,  G11C11/40611

Abstract: Memory with partial array density security is disclosed herein. In one embodiment, an apparatus comprises a memory region including a plurality of memory rows, a plurality of memory columns, and a plurality of memory cells arranged at intersections of the plurality of memory rows and the plurality of memory columns. The plurality of memory rows includes a plurality of enabled memory rows and a plurality of disabled memory rows. Sets of one or more disabled memory rows are interleaved with enabled memory rows within the memory region. To write data to or read data from the memory region, the apparatus can be configured to access only the enabled memory rows of the memory region. The apparatus may further be configured to refresh disabled memory rows of the memory region according to a different refresh protocol from a refresh protocol used to refresh the enabled memory rows of the memory region.

公开(公告)号：US20200349995A1

公开(公告)日：2020-11-05

申请号：US16936297

申请日：2020-07-22

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Michael A. Shore ,  Jiyun Li

IPC: G11C11/406 ,  G11C11/407 ,  G11C11/4076

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for managing access counts of wordlines of a memory. Repeated access to an aggressor wordline may cause increased data degradation in nearby victim wordlines of the memory. The access count of a given wordline may be stored in counter memory cells positioned along that wordline. When the wordline is accessed, the counter memory cells may be read out to refresh circuit, which may determine the access count based on the values stored in the counter memory cells. If the access count is below a threshold, the access count may be incremented and written back to the counter memory cells. If the access count is above the threshold, the refresh circuit may signal that the accessed wordline is an aggressor, and may reset the value of the access count before writing it back to the counter memory cells.

公开(公告)号：US20200312384A1

公开(公告)日：2020-10-01

申请号：US16372000

申请日：2019-04-01

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Shinichi Miyatake ,  Michael A. Shore ,  Adam J. Grenzebach

IPC: G11C7/08 ,  G11C11/4091

Abstract: Apparatuses and methods for compensation of sense amplifiers, for example, threshold voltage compensation, are disclosed. Prime memory sense amplifiers used for accessing prime memory and redundant memory sense amplifiers used for accessing redundant memory are concurrently compensated while determining whether a memory address is remapped from prime memory to redundant memory. Following the determination, sense amplifiers (e.g., prime memory sense amplifiers and/or redundant memory sense amplifiers) that are not used for accessing the memory corresponding to the memory address are precharged.

公开(公告)号：US20180315466A1

公开(公告)日：2018-11-01

申请号：US15583023

申请日：2017-05-01

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Huy T. Vo ,  Patrick Mullarkey ,  Jeffrey P. Wright ,  Michael A. Shore

IPC: G11C11/4091 ,  G11C11/406 ,  G11C11/4072 ,  G11C11/4094 ,  G11C11/4096

CPC classification number: G11C11/4091 ,  G11C11/40615 ,  G11C11/4072 ,  G11C11/4094 ,  G11C11/4096

Abstract: Systems and methods are provided for implementing an array rest mode. An example system includes at least one mode register configured to enable an array reset mode, a memory cell array including one or more sense amplifiers, and control logic. Each of the one or more sense amplifier may include at least a first terminal coupled to a first bit line and a second terminal coupled to a second bit line. The control logic may be coupled to the memory cell array, and in communication with the at least one mode register. The control logic may be configured to drive, in response to array reset mode being enabled, each of the first and second terminals of the sense amplifier to a bit-line precharge voltage that corresponds to a bit value to be written to respective memory cells associated with each of the first and second bit lines.

公开(公告)号：US11670356B2

公开(公告)日：2023-06-06

申请号：US17305878

申请日：2021-07-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yoshinori Fujiwara ,  Harish V. Gadamsetty ,  Gary Howe ,  Dennis G. Montierth ,  Michael A. Shore ,  Jason M. Johnson

IPC: G11C11/406 ,  G11C11/408 ,  G11C29/44 ,  G11C29/00 ,  G11C29/12

CPC classification number: G11C11/40622 ,  G11C11/4085 ,  G11C11/4087 ,  G11C29/4401 ,  G11C29/787 ,  G11C2029/1202

Abstract: Apparatuses, systems, and methods for refresh address masking. A memory device may refresh word lines as part of refresh operation by cycling through the word lines in a sequence. However, it may be desirable to avoid activating certain word lines (e.g., because they are defective). Refresh masking logic for each bank may include a fuse latch which stores a selected address associated with a word line to avoid. When a refresh address is generated it may be compared to the selected address. If there is a match, a refresh stop signal may be activated, which may prevent refreshing of the word line(s).

公开(公告)号：US20150082106A1

公开(公告)日：2015-03-19

申请号：US14518734

申请日：2014-10-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Michael A. Shore

IPC: G11C29/44 ,  G11C29/36

CPC classification number: G11C29/44 ,  G11C29/36 ,  G11C29/38 ,  G11C29/4401 ,  G11C29/883 ,  G11C2229/723

Abstract: Testing systems and methods, as well as memory devices using such testing systems and methods, may facilitate testing of memory devices using a read-modify-write test procedure. One such testing system receives a signal indicative of at least some of a plurality of bits of data read from an address differing from each other, and then masks subsequent write operations at the same address. Therefore, any address at which the bits of read data do not all have the same value may be considered to be faulty. Failure data from the test can therefore be stored in the same array of memory cells that is being tested.

Abstract translation: 使用这种测试系统和方法的测试系统和方法以及存储器件可以使用读 - 修改 - 写测试程序来促进对存储器件的测试。 一个这样的测试系统接收指示从彼此不同的地址读取的多个数据位中的至少一些的信号，然后在相同的地址处屏蔽后续的写入操作。 因此，读取数据的比特并不都具有相同值的任何地址可能被认为是有缺陷的。 因此，测试中的故障数据可以存储在正在测试的同一阵列的存储单元中。

公开(公告)号：US08964494B2

公开(公告)日：2015-02-24

申请号：US13850502

申请日：2013-03-26

Applicant: Micron Technology, Inc.

Inventor： Michael S. Lane ,  Michael A. Shore

IPC: G11C7/14 ,  G11C7/06 ,  G11C29/04 ,  G11C29/00

CPC classification number: G11C29/04 ,  G11C7/06 ,  G11C29/808

Abstract: A memory with extra digit lines in full size end arrays with an open digit architecture, which can use the extra digit lines to form repair cells. In one example, folded digit sense amplifiers are connected to an end array with an open digit architecture such that each sense amplifier corresponds to a group of four digit lines. Two digit lines of the group connect to two open digit sense amplifiers and the other two digit lines connect to the corresponding folded digit sense amplifier. A repair method can be performed on memories including the end arrays with folded digit sense amplifiers. A row in a core array including a replaceable IO is activated and a row in an end array is activated. The repair cells in the end array can be sensed by the folded digit sense amplifiers to generate a replacement IO, which is selected rather than the replaceable IO.

Abstract translation: 具有开放数字体系结构的全尺寸终端阵列中的额外数字线的存储器，可以使用额外的数字线形成修复单元。 在一个示例中，折叠数字读出放大器连接到具有开放数字架构的端部阵列，使得每个读出放大器对应于一组四位数字线。 该组的两位数字线连接到两个开放数字读出放大器，另外两个数字线连接到相应的折叠数字读出放大器。 可以对包括具有折叠数字读出放大器的端阵列的存储器执行修复方法。 激活包含可替换IO的核心阵列中的一行，并激活末端阵列中的一行。 结束阵列中的修复单元可以被折叠的数字读出放大器感测以产生替换IO，而不是可更换的IO。