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    Security memory scheme
    1.
    发明授权
    Security memory scheme 有权

    公开(公告)号：US11050569B2

    公开(公告)日：2021-06-29

    申请号：US16541009

    申请日：2019-08-14

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Chia-Jung Chen ,  Chin-Hung Chang ,  Kuen-Long Chang

    IPC: H04L29/06 ,  H04L9/32 ,  G06F3/06

    Abstract: A memory device can include a memory, and an interface to receive a memory command sequence. A message authentication code MAC is provided with the command sequence. Control circuits on the device include a command decoder to decode a received command sequence and to execute an identified memory operation. A message authentication engine includes logic to compute a value of a message authentication code to be matched with the received message authentication code based on the received command sequence and a stored key. The device can store a plurality of keys associated with one or more memory zones in the memory. Logic on the device prevents completion of the memory operation identified by the command sequence if the value computed does not match the received message authentication code.

    Memory device and associated control method
    2.
    发明授权
    Memory device and associated control method 有权

    公开(公告)号：US12197745B2

    公开(公告)日：2025-01-14

    申请号：US17817711

    申请日：2022-08-05

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Chin-Hung Chang ,  Chia-Jung Chen ,  Ken-Hui Chen ,  Chun-Hsiung Hung

    IPC: G06F3/06

    Abstract: A memory device and an associated control method are provided. The memory device includes a non-volatile memory array and a memory control circuit. The non-volatile memory array includes M secured memory zones. The memory control circuit is electrically connected to the non-volatile memory array. The memory control circuit provides a set of mapping information and searches a request key in the set of mapping information. The set of mapping information represents correspondences between N access keys and the M secured memory zones. The memory control circuit acquires at least one of the M secured memory zones if the request key is one of the N access keys, and performs an access command to the at least one of the M secured memory zones. M and N are positive integers.

    Multi-chip package, controlling method of multi-chip package and security chip
    3.
    发明申请
    Multi-chip package, controlling method of multi-chip package and security chip 审中-公开

    公开(公告)号：US20200057575A1

    公开(公告)日：2020-02-20

    申请号：US15998456

    申请日：2018-08-15

    Applicant: Macronix International Co., Ltd.

    Inventor： Chia-Jung Chen ,  Chin-Hung Chang ,  Ken-Hui Chen

    IPC: G06F3/06

    Abstract: A multi-chip package, a controlling method of the multi-chip package and a security chip are provided. The multi-chip package includes a memory chip and a security chip. The security chip is coupled between the memory chip and a host. The security chip includes a processing circuit. The processing circuit is for enabling a security path to input an input-output signal into the processing circuit for executing a security procedure and accessing the memory chip, if a command is received by the processing circuit and the command includes a security requirement.

    Memory with dynamic permissible bit write logic and method
    6.
    发明授权
    Memory with dynamic permissible bit write logic and method 有权

    公开(公告)号：US10032511B1

    公开(公告)日：2018-07-24

    申请号：US15599350

    申请日：2017-05-18

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Chun-Hsiung Hung ,  Chia-Jung Chen

    IPC: G11C13/00

    Abstract: For a memory array including a plurality of bit lines, and a set of write drivers having a number N members configured for connection in parallel to a selected set of N bit lines in the plurality of bit lines, write logic is coupled to the set of write drivers which enables a permissible number less than said number N of said members of the set of write drivers to apply a write pulse in parallel in a write operation. The write logic can dynamically assign permissible numbers to iterations in an iterative write sequence. A power source, such as charge pump circuitry, coupled to the set of write drivers can be utilized more efficiently in systems applying permissible bit write logic, enabling higher throughput or utilizing lower peak power.

    MEMORY DEVICE AND READ OPERATION METHOD THEREOF
    7.
    发明申请
    MEMORY DEVICE AND READ OPERATION METHOD THEREOF 有权
    存储器件及其读取操作方法

    公开(公告)号：US20150023120A1

    公开(公告)日：2015-01-22

    申请号：US14506768

    申请日：2014-10-06

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Chin-Hung Chang ,  Chia-Jung Chen ,  Su-Chueh Lo ,  Ken-Hui Chen ,  Kuen-Long Chang

    IPC: G11C7/10 ,  G11C7/12 ,  G11C7/06

    CPC classification number: G11C7/1048 ,  G11C7/06 ,  G11C7/08 ,  G11C7/106 ,  G11C7/12 ,  G11C7/18 ,  G11C2207/002

    Abstract: A read operation for a memory device is provided. A selected word line, first and second global bit line groups and a selected first bit line group are precharged. A first cell current flowing through the selected word line, the first and the selected first bit line groups is generated. A first reference current flowing through the second global bit line group is generated. A first half page data is read based on the first cell current and the first reference current. The selected word line, the first and the second global bit line groups are kept precharged.

    Abstract translation: 提供了存储器件的读取操作。 选择的字线，第一和第二全局位线组和所选择的第一位线组被预先充电。 流过所选字线的第一单元电流，产生第一和所选择的第一位线组。 产生流过第二全局位线组的第一参考电流。 基于第一单元电流和第一参考电流来读取前​​半页数据。 所选择的字线，第一和第二全局位线组保持预充电。

    MANAGING STATUS OUTPUT
    9.
    发明公开
    MANAGING STATUS OUTPUT 审中-公开

    公开(公告)号：US20240184668A1

    公开(公告)日：2024-06-06

    申请号：US18191401

    申请日：2023-03-28

    Applicant: Macronix International Co., Ltd.

    Inventor： Chin-Hung Chang ,  Chia-Jung Chen ,  Ken-Hui Chen

    IPC: G06F11/10

    CPC classification number: G06F11/1044

    Abstract: Systems, devices, methods, and circuits for managing status output are provided. In one aspect, a semiconductor device includes: a memory array configured to store data and a circuitry coupled to the memory array and configured to execute a read operation in the memory array and output a read packet based on a result of the execution of the read operation. The read packet includes readout data and error information associated with the readout data. The error information is indicated by at least one of an error code or one or more secure codes in the read packet.

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