公开(公告)号：US09558823B1

公开(公告)日：2017-01-31

申请号：US14846393

申请日：2015-09-04

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Win-San Khwa ,  Tzu-Hsiang Su ,  Chao-I Wu ,  Hsiang-Pan Li ,  Meng-Fan Chang

IPC: G11C11/00 ,  G11C13/00 ,  G11C11/56

CPC classification number: G11C13/0069 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0021 ,  G11C13/0033 ,  G11C13/004 ,  G11C2013/0092

Abstract: A method is provided for operating a memory device including an array of memory cells including programmable resistive memory elements. Memory cells in the array are programmed to store data by applying program pulses to the memory cells to establish resistance levels within a number N of specified ranges of resistance, where each of the specified ranges corresponds to a particular data value. A drift recovery process is executed to the memory cells, including applying a recovery pulse having a pulse shape to a set of programmed memory cells, where memory cells in the set have resistance levels within two or more of the specified resistance ranges.

Abstract translation: 提供一种用于操作包括包括可编程电阻存储器元件的存储单元阵列的存储器件的方法。 阵列中的存储单元被编程为通过向存储器单元施加编程脉冲来存储数据，以建立指定范围电阻数量N内的电阻电平，其中每个指定范围对应于特定数据值。 对存储器单元执行漂移恢复处理，包括将具有脉冲形状的恢复脉冲施加到一组编程存储器单元，其中该组中的存储单元具有在指定电阻范围内的两个或更多个内的电阻电平。

公开(公告)号：US09548135B2

公开(公告)日：2017-01-17

申请号：US14055656

申请日：2013-10-16

Applicant: Macronix International Co., Ltd.

Inventor： Yih-Shan Yang ,  Shou-Nan Hung ,  Chun-Hsiung Hung ,  Yao-Jen Kuo ,  Meng-Fan Chang

IPC: G11C29/00 ,  G06F11/07 ,  G11C29/02 ,  G06F11/08 ,  G11C29/42 ,  G11C29/44 ,  G11C16/26

CPC classification number: G06F11/076 ,  G06F3/0619 ,  G06F3/0656 ,  G06F3/0679 ,  G06F11/0727 ,  G06F11/0787 ,  G06F11/08 ,  G11C16/08 ,  G11C16/26 ,  G11C16/3445 ,  G11C16/3459 ,  G11C29/00 ,  G11C29/022 ,  G11C29/42 ,  G11C29/44 ,  G11C2216/14

Abstract: Counting status circuits are electrically coupled to corresponding status elements. The status elements selectably store a bit status of a bit line coupled to a memory array. The bit status can indicate one of at least pass and fail. The counting status circuits are electrically coupled to each other in a sequential order. Control logic causes processing of the counting status circuits in the sequential order to determine a total of the memory elements that store the bit status. The total number of memory elements that store the bit status indicate the number of error bits or non-error bits, which can help determine whether there are too many errors to be fixed by error correction codes.

Abstract translation: 计数状态电路电耦合到相应的状态元件。 状态元件可选地存储耦合到存储器阵列的位线的位状态。 位状态可以指示至少通过和失败。 计数状态电路按顺序相互电耦合。 控制逻辑使得按顺序处理计数状态电路以确定存储位状态的存储元件的总数。 存储位状态的存储元件的总数表示错误位数或非错误位的数量，这可以帮助确定错误校正码是否存在太多的错误。

公开(公告)号：US20140258794A1

公开(公告)日：2014-09-11

申请号：US14055656

申请日：2013-10-16

Applicant: Macronix International Co., Ltd.

Inventor： Yih-Shan Yang ,  Shou-Nan Hung ,  Chun-Hsiung Hung ,  Yao-Jen Kuo ,  Meng-Fan Chang

IPC: G06F11/07

CPC classification number: G06F11/076 ,  G06F3/0619 ,  G06F3/0656 ,  G06F3/0679 ,  G06F11/0727 ,  G06F11/0787 ,  G06F11/08 ,  G11C16/08 ,  G11C16/26 ,  G11C16/3445 ,  G11C16/3459 ,  G11C29/00 ,  G11C29/022 ,  G11C29/42 ,  G11C29/44 ,  G11C2216/14

Abstract: Counting status circuits are electrically coupled to corresponding status elements. The status elements selectably store a bit status of a bit line coupled to a memory array. The bit status can indicate one of at least pass and fail. The counting status circuits are electrically coupled to each other in a sequential order. Control logic causes processing of the counting status circuits in the sequential order to determine a total of the memory elements that store the bit status. The total number of memory elements that store the bit status indicate the number of error bits or non-error bits, which can help determine whether there are too many errors to be fixed by error correction codes.

Abstract translation: 计数状态电路电耦合到相应的状态元件。 状态元件可选地存储耦合到存储器阵列的位线的位状态。 位状态可以指示至少通过和失败。 计数状态电路按顺序相互电耦合。 控制逻辑使得按顺序处理计数状态电路以确定存储位状态的存储元件的总数。 存储位状态的存储元件的总数表示错误位数或非错误位的数量，这可以帮助确定错误纠正码是否存在太多的错误。

公开(公告)号：US10481965B2

公开(公告)日：2019-11-19

申请号：US15389238

申请日：2016-12-22

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yih-Shan Yang ,  Shou-Nan Hung ,  Chun-Hsiung Hung ,  Yao-Jen Kuo ,  Meng-Fan Chang

IPC: G06F11/07 ,  G11C16/08 ,  G11C16/34 ,  G06F3/06 ,  G06F11/08 ,  G11C29/00 ,  G11C29/02 ,  G11C29/42 ,  G11C29/44 ,  G11C16/26

Abstract: Counting status circuits are electrically coupled to corresponding status elements. The status elements selectably store a bit status of a bit line coupled to a memory array. The bit status can indicate one of at least pass and fail. The counting status circuits are electrically coupled to each other in a sequential order. Control logic causes processing of the counting status circuits in the sequential order to determine a total of the memory elements that store the bit status. The total number of memory elements that store the bit status indicate the number of error bits or non-error bits, which can help determine whether there are too many errors to be fixed by error correction codes.