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1.发明授权公开(公告)号：US07811891B2
公开(公告)日：2010-10-12
申请号：US11331958
申请日：2006-01-13
IPC分类号： H01L21/336
CPC分类号： H01L21/28114 , H01L29/42376 , H01L29/6659 , H01L29/7833
摘要： A semiconductor process and apparatus uses a predetermined sequence of patterning and etching steps to etch a gate stack (30, 32) formed over a substrate (36), thereby forming an etched gate (33) having a vertical sidewall profile (35). By constructing the gate stack (30, 32) with a graded material composition of silicon-based layers, the composition of which is selected to counteract the etching tendencies of the predetermined sequence of patterning and etching steps, a more idealized vertical gate sidewall profile (35) may be obtained.
摘要翻译： 半导体工艺和设备使用预定的图案化和蚀刻步骤序列来蚀刻在衬底（36）上形成的栅极堆叠（30,32），由此形成具有垂直侧壁轮廓（35）的蚀刻栅极（33）。 通过用硅基层的分级材料组成构造栅极堆叠（30,32），其组成被选择以抵消预定的图案化和蚀刻步骤的蚀刻趋势，更理想的垂直栅极侧壁轮廓（ 35）。
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2.发明授权Semiconductor process for forming stress absorbent shallow trench isolation structures 有权用于形成应力吸收性浅沟槽隔离结构的半导体工艺公开(公告)号：US07442621B2
公开(公告)日：2008-10-28
申请号：US10996319
申请日：2004-11-22
IPC分类号： H01L21/76
CPC分类号： H01L29/7842 , H01L21/76224 , H01L21/76229 , H01L21/823807 , H01L21/823878
摘要： A semiconductor fabrication process includes patterning a hard mask over a semiconductor substrate to expose an isolation region and forming a trench in the isolation region. A flowable dielectric is deposited in the trench to partially fill the trench and a capping dielectric is deposited overlying the first oxide to fill the trench. The substrate may be a silicon on insulator (SOI) substrate including a buried oxide (BOX) layer and the trench may extend partially into the BOX layer. The flowable dielectric may be a spin deposited flowable oxide or a CVD BPSG oxide. The flowable dielectric isolation structure provides a buffer that prevents stress induced on one side of the isolation structure from creating stress on the other side of the structure. Thus, for example, compressive stress created by forming silicon germanium on silicon in PMOS regions does not create compressive stress in NMOS regions.
摘要翻译： 半导体制造工艺包括在半导体衬底上图案化硬掩模以暴露隔离区域并在隔离区域中形成沟槽。 在沟槽中沉积可流动电介质以部分地填充沟槽，并且覆盖覆盖第一氧化物的覆盖电介质以填充沟槽。 衬底可以是包括掩埋氧化物（BOX）层的绝缘体上硅（SOI）衬底，并且沟槽可以部分地延伸到BOX层中。 可流动电介质可以是自旋沉积的可流动氧化物或CVD BPSG氧化物。 可流动介电隔离结构提供了缓冲器，其防止在隔离结构的一侧上引起的应力在结构的另一侧上产生应力。 因此，例如，通过在PMOS区域中的硅上形成硅锗产生的压缩应力在NMOS区域中不产生压应力。
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3.发明授权Method for forming a semiconductor device with local semiconductor-on-insulator (SOI) 有权用局部绝缘体半导体（SOI）形成半导体器件的方法公开(公告)号：US07045432B2
公开(公告)日：2006-05-16
申请号：US10771855
申请日：2004-02-04
CPC分类号： H01L29/66772 , H01L29/785 , H01L29/78603
摘要： A semiconductor on insulator transistor is formed beginning with a bulk silicon substrate. An active region is defined in the substrate and an oxygen-rich silicon layer that is monocrystalline is formed on a top surface of the active region. On this oxygen-rich silicon layer is grown an epitaxial layer of silicon. After formation of the epitaxial layer of silicon, the oxygen-rich silicon layer is converted to silicon oxide while at least a portion of the epitaxial layer of silicon remains as monocrystalline silicon. This is achieved by applying high temperature water vapor to the epitaxial layer. The result is a silicon on insulator structure useful for making a transistor in which the gate dielectric is on the remaining monocrystalline silicon, the gate is on the gate dielectric, and the channel is in the remaining monocrystalline silicon under the gate.
摘要翻译： 半导体绝缘体晶体管以体硅衬底开始形成。 在衬底中限定有源区，并且在有源区的顶表面上形成单晶的富氧硅层。 在该富氧硅层上生长硅的外延层。 在形成硅的外延层之后，将富氧硅层转化为氧化硅，而硅的外延层的至少一部分保留为单晶硅。 这通过将高温水蒸气施加到外延层来实现。 结果是用于制造晶体管的绝缘体上硅结构，其中栅极电介质位于剩余的单晶硅上，栅极位于栅极电介质上，沟道位于栅极之下的剩余单晶硅中。
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公开(公告)号：US07037795B1
公开(公告)日：2006-05-02
申请号：US10965964
申请日：2004-10-15
申请人： Alexander L. Barr , Olubunmi O. Adetutu , Bich-Yen Nguyen , Marius K. Orlowski , Mariam G. Sadaka , Voon-Yew Thean , Ted R. White
发明人： Alexander L. Barr , Olubunmi O. Adetutu , Bich-Yen Nguyen , Marius K. Orlowski , Mariam G. Sadaka , Voon-Yew Thean , Ted R. White
IPC分类号： H01L21/336
CPC分类号： H01L29/66772 , H01L29/66636 , H01L29/78618
摘要： A semiconductor fabrication process includes forming a transistor gate overlying an SOI wafer having a semiconductor top layer over a buried oxide layer (BOX) over a semiconductor substrate. Source/drain trenches, disposed on either side of the gate, are etched into the BOX layer. Source/drain structures are formed within the trenches. A depth of the source/drain structures is greater than the thickness of the top silicon layer and an upper surface of the source/drain structures coincides approximately with the transistor channel whereby vertical overlap between the source/drain structures and the gate is negligible. The trenches preferably extend through the BOX layer to expose a portion of the silicon substrate. The source/drain structures are preferably formed epitaxially and possibly in two stages including an oxygen rich stage and an oxygen free stage. A thermally anneal between the two epitaxial stages will form an isolation dielectric between the source/drain structure and the substrate.
摘要翻译： 半导体制造工艺包括在半导体衬底上的掩埋氧化物层（BOX）上形成半导体顶层的SOI晶片的晶体管栅极。 设置在栅极两侧的源极/漏极沟槽被蚀刻到BOX层中。 源极/漏极结构形成在沟槽内。 源极/漏极结构的深度大于顶部硅层的厚度，并且源极/漏极结构的上表面大致与晶体管沟道重合，源极/漏极结构与栅极之间的垂直重叠可忽略不计。 沟槽优选地延伸穿过BOX层以暴露硅衬底的一部分。 源极/漏极结构优选外延地形成，并且可能包括富氧阶段和无氧阶段的两个阶段。 两个外延级之间的热退火将在源极/漏极结构和衬底之间形成隔离电介质。
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公开(公告)号：US07288458B2
公开(公告)日：2007-10-30
申请号：US11302770
申请日：2005-12-14
IPC分类号： H01L21/331 , H01L21/8222
CPC分类号： H01L21/76254 , H01L21/02002
摘要： A wafer having an SOI configuration and active regions having different surface orientations for different channel type transistors. In one example, semiconductor structures having a first surface orientation are formed on a donor wafer. Semiconductor structures having a second surface orientation are formed on a second wafer. Receptor openings are formed on the second wafer. The semiconductor structures having the first surface orientation are located in the receptor openings and transferred to the second wafer. The resultant wafer has semiconductor regions having a first surface orientation for a first channel type of transistor and semiconductor regions having a second surface orientation for a second channel type transistor.
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6.发明授权Dual metal gate electrode semiconductor fabrication process and structure thereof 失效双金属栅电极半导体制造工艺及其结构公开(公告)号：US07074664B1
公开(公告)日：2006-07-11
申请号：US11092418
申请日：2005-03-29
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842
摘要： A semiconductor fabrication process includes patterning a first gate electrode layer overlying a gate dielectric. A second gate electrode layer is formed overlying the first gate electrode layer and the gate dielectric. Portions of the second gate electrode layer overlying the first gate electrode layer are removed until the first and second gate electrode layers have the same thickness. A third gate electrode layer may be formed overlying the first and second gate electrode layers. The first gate electrode layer may comprise TiN and reside primarily overlying PMOS regions while the second gate electrode layer may comprise TaC or TaSiN and primarily overlie NMOS regions. Removing portions of the second gate electrode layer may include performing a chemical mechanical process (CMP) without masking the second gate electrode layer or forming a resist mask and etching exposed portions of the second gate electrode layer.
摘要翻译： 半导体制造工艺包括图案化覆盖栅极电介质的第一栅极电极层。 第二栅极电极层形成在第一栅极电极层和栅极电介质上。 去除覆盖在第一栅极电极层上的第二栅极电极层的部分，直到第一和第二栅电极层具有相同的厚度。 可以形成第三栅极电极层，覆盖第一和第二栅电极层。 第一栅极电极层可以包括TiN并且主要驻留在PMOS区域上，而第二栅极电极层可以包括TaC或TaSiN并且主要覆盖NMOS区域。 去除第二栅极电极层的部分可以包括在不掩蔽第二栅电极层或形成抗蚀剂掩模并蚀刻第二栅电极层的暴露部分的情况下执行化学机械处理（CMP）。
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7.发明授权公开(公告)号：US07071038B2
公开(公告)日：2006-07-04
申请号：US10946938
申请日：2004-09-22
IPC分类号： H01L21/84
CPC分类号： H01L21/28185 , H01L21/3213 , H01L29/513 , H01L29/517 , Y10S438/977 , Y10S438/981
摘要： A method for forming a semiconductor device (10) creates a dielectric layer (18) with high dielectric constant. An interfacial layer (14) is formed over a semiconductor substrate (12). A dielectric layer (16) is formed over the interfacial layer, wherein the dielectric layer has a high dielectric constant (K). The dielectric layer is thinned, such as by etching or chemical mechanical polishing, wherein a thickness of the thinned dielectric layer is less than a thickness of the dielectric layer prior to thinning. In one form, the method is used to form a transistor having a gate electrode layer formed over the thinned dielectric layer and source/drain diffusions (24, 26) within the semiconductor substrate.
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公开(公告)号：US07030001B2
公开(公告)日：2006-04-18
申请号：US10827202
申请日：2004-04-19
IPC分类号： H01L21/3205
CPC分类号： H01L21/823842 , B82Y10/00 , B82Y30/00 , C23C16/042 , H01L21/28079 , H01L29/495 , H01L29/4958 , H01L29/7833
摘要： One embodiment forms a gate dielectric layer over a substrate and then selectively deposits a first metal layer over portions of the gate dielectric layer in which a first device type will be formed. A second metal layer, different from the first metal layer, is formed over exposed portions of the gate dielectric layer in which a second device type will be formed. Each of the first and second device types will have different work functions because each will include a different metal in direct contact with the gate dielectric. In one embodiment, the selective deposition of the first metal layer is performed by ALD and with the use of an inhibitor layer which is selectively formed over the gate dielectric layer such that the first metal layer may be selectively deposited on only those portions of the gate dielectric layer which are not covered by the inhibitor layer.
摘要翻译： 一个实施例在衬底上形成栅极电介质层，然后在其中将形成第一器件类型的栅极电介质层的部分上选择性地沉积第一金属层。 不同于第一金属层的第二金属层形成在将形成第二器件类型的栅极电介质层的暴露部分上。 第一和第二装置类型中的每一种将具有不同的功函数，因为每个将包括与栅极电介质直接接触的不同金属。 在一个实施例中，第一金属层的选择性沉积由ALD执行，并且使用抑制层，其选择性地形成在栅极电介质层上，使得第一金属层可以仅选择性地沉积在栅极的那些部分 未被抑制层覆盖的介电层。
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9.发明授权Semiconductor process and integrated circuit having dual metal oxide gate dielectric with single metal gate electrode 有权具有双金属氧化物栅极电介质和单金属栅电极的半导体工艺和集成电路公开(公告)号：US06897095B1
公开(公告)日：2005-05-24
申请号：US10843850
申请日：2004-05-12
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857
摘要： A semiconductor fabrication process includes forming first and second transistors over first and second well regions, respectively where the first transistor has a first gate dielectric and the second transistor has a second gate dielectric different from the first gate dielectric. The first transistor has a first gate electrode and the second transistor has a second gate electrode. The first and second gate electrodes are the same in composition. The first gate dielectric and the second gate dielectric may both include high-K dielectrics such as Hafnium oxide and Aluminum oxide. The first and second gate electrodes both include a gate electrode layer overlying the respective gate dielectrics. The gate electrode layer is preferably either TaSiN and TaC. The first and second gate electrodes may both include a conductive layer overlying the gate electrode layer. In one such embodiment, the conductive layer may include polysilicon and tungsten.
摘要翻译： 半导体制造工艺包括在第一和第二阱区域分别形成第一和第二晶体管，其中第一晶体管具有第一栅极电介质，而第二晶体管具有不同于第一栅极电介质的第二栅极电介质。 第一晶体管具有第一栅电极，第二晶体管具有第二栅电极。 第一和第二栅电极的组成相同。 第一栅极电介质和第二栅极电介质可以都包括高K电介质，例如氧化铪和氧化铝。 第一和第二栅电极都包括覆盖各个栅极电介质的栅极电极层。 栅电极层优选为TaSiN和TaC。 第一和第二栅电极都可以包括覆盖栅电极层的导电层。 在一个这样的实施例中，导电层可以包括多晶硅和钨。
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公开(公告)号：US06790719B1
公开(公告)日：2004-09-14
申请号：US10410043
申请日：2003-04-09
IPC分类号： H01L21337
CPC分类号： H01L21/823468 , H01L21/82345 , H01L21/823462
摘要： A semiconductor device has a P channel gate stack comprising a first metal type and a second metal type over the first metal type and an N channel gate stack comprising the second metal type in direct contact with the a gate dielectric. The N channel gate stack and a portion of the P channel gate stack are etched by a dry etch. The etch of P channel gate stack is completed with a wet etch. The wet etch is very selective to the gate dielectric and to the second metal type so that the N channel transistor is not adversely effected by completing the etch of the P channel gate stack.
摘要翻译： 半导体器件具有包括第一金属类型的第一金属类型和第二金属类型的P沟道栅极堆叠以及包括与栅极电介质直接接触的第二金属类型的N沟道栅极堆叠。 通过干蚀刻来蚀刻N沟道栅极堆叠和P沟道栅极堆叠的一部分。 通过湿式蚀刻完成P沟道栅叠层的蚀刻。 湿蚀刻对栅极电介质和第二金属类型是非常选择的，使得N沟道晶体管不会通过完成P沟道栅极堆叠的蚀刻而受到不利影响。
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