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1.发明授权公开(公告)号：US07071038B2
公开(公告)日：2006-07-04
申请号：US10946938
申请日：2004-09-22
IPC分类号： H01L21/84
CPC分类号： H01L21/28185 , H01L21/3213 , H01L29/513 , H01L29/517 , Y10S438/977 , Y10S438/981
摘要： A method for forming a semiconductor device (10) creates a dielectric layer (18) with high dielectric constant. An interfacial layer (14) is formed over a semiconductor substrate (12). A dielectric layer (16) is formed over the interfacial layer, wherein the dielectric layer has a high dielectric constant (K). The dielectric layer is thinned, such as by etching or chemical mechanical polishing, wherein a thickness of the thinned dielectric layer is less than a thickness of the dielectric layer prior to thinning. In one form, the method is used to form a transistor having a gate electrode layer formed over the thinned dielectric layer and source/drain diffusions (24, 26) within the semiconductor substrate.
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公开(公告)号：US08404594B2
公开(公告)日：2013-03-26
申请号：US11139765
申请日：2005-05-27
IPC分类号： C23F1/00 , H01L21/461 , H01L21/302 , B44C1/22
CPC分类号： H01L21/0228 , H01L21/02142 , H01L21/02175 , H01L21/265 , H01L21/31111 , H01L21/31116 , H01L21/31122 , H01L21/3141 , H01L21/31645 , H01L21/823462 , H01L21/823857 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/78
摘要： A semiconductor process and apparatus includes forming first and second gate electrodes (151, 161) by forming the first gate electrode (151) over a first high-k gate dielectric (121) and forming the second gate electrode (161) over at least a second high-k gate dielectric (122) different from the first gate dielectric (121). Either or both of the high-k gate dielectric layers (121, 122) may be formed by depositing and selectively etching an initial layer of high-k dielectric material (e.g., 14). As deposited, the initial layer (14) has an exposed surface (18) and an initial predetermined crystalline structure. An exposed thin surface layer (20) of the initial layer (14) is prepared for etching by modifying the initial crystalline structure in the exposed thin surface layer. The modified crystalline structure in the exposed thin surface layer may be removed by applying a selective etch, such as HF or HCl.
摘要翻译： 半导体工艺和装置包括通过在第一高k栅极电介质（121）上形成第一栅电极（151）并且形成第二栅极电极（161）至少形成第一栅极电极（151,161） 与第一栅极电介质（121）不同的第二高k栅极电介质（122）。 可以通过沉积和选择性蚀刻高k电介质材料的初始层（例如14）来形成高k栅极电介质层（121,122）之一或两者。 沉积时，初始层（14）具有暴露表面（18）和初始预定晶体结构。 通过改变暴露的薄表面层中的初始晶体结构，准备初始层（14）的暴露的薄表面层（20）用于蚀刻。 暴露的薄表面层中的改性晶体结构可以通过施加选择性蚀刻如HF或HCl来去除。
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3.发明授权Plasma treatment of a semiconductor surface for enhanced nucleation of a metal-containing layer 有权用于增强含金属层成核的半导体表面的等离子体处理公开(公告)号：US08030220B2
公开(公告)日：2011-10-04
申请号：US12579072
申请日：2009-10-14
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/02315 , H01L21/02052 , H01L21/02142 , H01L21/02175 , H01L21/0228 , H01L21/28194 , H01L21/2822 , H01L21/306 , H01L21/3141 , H01L29/513 , H01L29/517 , H01L29/518
摘要： A method for forming a dielectric layer is provided. The method may include providing a semiconductor surface and etching a thin layer of the semiconductor substrate to expose a surface of the semiconductor surface, wherein the exposed surface is hydrophobic. The method may further include treating the exposed surface of the semiconductor substrate with plasma to neutralize a hydrophobicity associated with the exposed surface, wherein the exposed surface is treated using plasma with a power in a range of 100 watts to 500 watts and for duration in a range of 1 to 60 seconds. The method may further include forming a metal-containing layer on a top surface of the plasma treated surface using an atomic layer deposition process.
摘要翻译： 提供一种形成电介质层的方法。 该方法可以包括提供半导体表面并蚀刻半导体衬底的薄层以暴露半导体表面的表面，其中暴露表面是疏水性的。 该方法可以进一步包括用等离子体处理半导体衬底的暴露表面以中和与暴露表面相关联的疏水性，其中暴露表面使用等离子体处理，功率范围为100瓦至500瓦，并且持续时间为 范围为1到60秒。 该方法可以进一步包括使用原子层沉积工艺在等离子体处理的表面的顶表面上形成含金属层。
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4.发明授权Plasma treatment of a semiconductor surface for enhanced nucleation of a metal-containing layer 有权用于增强含金属层成核的半导体表面的等离子体处理公开(公告)号：US07618902B2
公开(公告)日：2009-11-17
申请号：US11290320
申请日：2005-11-30
IPC分类号： H01L21/31 , H01L21/469 , H01L21/336
CPC分类号： H01L21/02315 , H01L21/02052 , H01L21/02142 , H01L21/02175 , H01L21/0228 , H01L21/28194 , H01L21/2822 , H01L21/306 , H01L21/3141 , H01L29/513 , H01L29/517 , H01L29/518
摘要： A method for forming a dielectric layer is provided. The method may include providing a semiconductor surface and etching a thin layer of the semiconductor substrate to expose a surface of the semiconductor surface, wherein the exposed surface is hydrophobic. The method may further include treating the exposed surface of the semiconductor substrate with plasma to neutralize a hydrophobicity associated with the exposed surface, wherein the exposed surface is treated using plasma with a power in a range of 100 watts to 500 watts and for duration in a range of 1 to 60 seconds. The method may further include forming a metal-containing layer on a top surface of the plasma treated surface using an atomic layer deposition process.
摘要翻译： 提供一种形成电介质层的方法。 该方法可以包括提供半导体表面并蚀刻半导体衬底的薄层以暴露半导体表面的表面，其中暴露表面是疏水性的。 该方法可以进一步包括用等离子体处理半导体衬底的暴露表面以中和与暴露表面相关联的疏水性，其中暴露表面使用等离子体处理，功率范围为100瓦至500瓦，并且持续时间为 范围为1到60秒。 该方法可以进一步包括使用原子层沉积工艺在等离子体处理的表面的顶表面上形成含金属层。
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公开(公告)号：US07704821B2
公开(公告)日：2010-04-27
申请号：US11146826
申请日：2005-06-07
IPC分类号： H01L21/8238
CPC分类号： H01L29/517 , H01L21/28194 , H01L21/28202 , H01L21/28229 , H01L29/513 , H01L29/518 , H01L29/78
摘要： A semiconductor fabrication process for forming a gate dielectric includes depositing a high-k dielectric stack including incorporating nitrogen into the high-k dielectric stack in-situ. A top high-k dielectric is formed overlying the dielectric stack and the dielectric stack and the top dielectric are annealed. Depositing the dielectric stack includes depositing a plurality of high-k dielectric layers where each layer is formed in a distinct processing step or set of steps. Depositing one of the dielectric layers includes performing a plurality of atomic layer deposition processes to form a plurality of high-k sublayers, wherein each sublayer is a monolayer film. Depositing the plurality of sublayers includes depositing a nitrogen free sublayer and depositing a nitrogen bearing sublayer. Depositing the nitrogen free sublayer includes pulsing an ALD chamber with HfCl4, purging the chamber with an inert, pulsing the chamber with an H2O or D2O, and purging the chamber with an inert.
摘要翻译： 用于形成栅极电介质的半导体制造工艺包括沉积高k电介质堆叠，其包括将氮掺杂到原位的高k电介质堆叠中。 形成覆盖在电介质堆叠上的顶部高k电介质，并且电介质堆叠和顶部电介质被退火。 沉积介电堆叠包括沉积多个高k电介质层，其中每个层以不同的处理步骤或一组步骤形成。 沉积一个电介质层包括执行多个原子层沉积工艺以形成多个高k子层，其中每个子层是单层膜。 沉积多个子层包括沉积无氮的子层并沉积含氮的子层。 沉积无氮子层包括用HfCl 4脉冲ALD室，用惰性气体冲洗室，用H 2 O或D 2 O脉冲室，并用惰性气体清洗室。
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6.发明申请PLASMA TREATMENT OF A SEMICONDUCTOR SURFACE FOR ENHANCED NUCLEATION OF A METAL-CONTAINING LAYER 有权用于增强含金属层的半导体表面的等离子体处理公开(公告)号：US20100035434A1
公开(公告)日：2010-02-11
申请号：US12579072
申请日：2009-10-14
IPC分类号： H01L21/31 , H01L21/306
CPC分类号： H01L21/02315 , H01L21/02052 , H01L21/02142 , H01L21/02175 , H01L21/0228 , H01L21/28194 , H01L21/2822 , H01L21/306 , H01L21/3141 , H01L29/513 , H01L29/517 , H01L29/518
摘要： A method for forming a dielectric layer is provided. The method may include providing a semiconductor surface and etching a thin layer of the semiconductor substrate to expose a surface of the semiconductor surface, wherein the exposed surface is hydrophobic. The method may further include treating the exposed surface of the semiconductor substrate with plasma to neutralize a hydrophobicity associated with the exposed surface, wherein the exposed surface is treated using plasma with a power in a range of 100 watts to 500 watts and for duration in a range of 1 to 60 seconds. The method may further include forming a metal-containing layer on a top surface of the plasma treated surface using an atomic layer deposition process.
摘要翻译： 提供一种形成电介质层的方法。 该方法可以包括提供半导体表面并蚀刻半导体衬底的薄层以暴露半导体表面的表面，其中暴露表面是疏水性的。 该方法可以进一步包括用等离子体处理半导体衬底的暴露表面以中和与暴露表面相关联的疏水性，其中暴露表面使用等离子体处理，功率范围为100瓦至500瓦，并且持续时间为 范围为1到60秒。 该方法可以进一步包括使用原子层沉积工艺在等离子体处理的表面的顶表面上形成含金属层。
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公开(公告)号：US07303983B2
公开(公告)日：2007-12-04
申请号：US11331763
申请日：2006-01-13
IPC分类号： H01L21/3205
CPC分类号： H01L21/28088 , H01L29/4966 , H01L29/517 , H01L29/665 , H01L29/6656 , H01L29/6659
摘要： A semiconductor process and apparatus fabricate a metal gate electrode by forming a first conductive layer (22) over a gate dielectric layer (11), forming a transition layer (32) over the first conductive layer using an atomic layer deposition process in which an amorphizing material is increasingly added as the transition layer is formed, forming a capping conductive layer (44) over the transition layer, and then selectively etching the capping conductive layer, transition layer, and first conductive layer, resulting in the formation of an etched gate stack (52). By forming the transition layer (32) with an atomic layer deposition process in which the amorphizing material (such as silicon, carbon, or nitrogen) is increasingly added, the transition layer (32) is constructed having a lower region (e.g., 31, 33) with a polycrystalline structure and an upper region (e.g., 37, 39) with an amorphous structure that blocks silicon diffusion.
摘要翻译： 一种半导体工艺和装置，通过在栅介质层（11）上形成第一导电层（22）制造金属栅电极，在第一导电层上形成过渡层（32），使用原子层沉积工艺，其中非晶化 随着形成过渡层，材料越来越多地加入，在过渡层上形成覆盖导电层（44），然后选择性地蚀刻覆盖导电层，过渡层和第一导电层，从而形成蚀刻栅叠层 （52）。 通过用原子层沉积工艺形成过渡层（32），其中非晶化材料（例如硅，碳或氮）越来越多地被加入，过渡层（32）被构造成具有较低的区域（例如，31， 33）和具有阻挡硅扩散的非晶结构的上部区域（例如，37,39）。
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8.发明授权公开(公告)号：US06987063B2
公开(公告)日：2006-01-17
申请号：US10865452
申请日：2004-06-10
IPC分类号： H01L21/44
CPC分类号： C23C14/0005 , C23C16/4401 , C23C16/56 , H01L21/3141 , H01L21/31604 , H01L21/31645
摘要： A metal-containing semiconductor layer having a high dielectric constant is formed with a method that avoids inclusion of contaminant elements that reduce dielectric constant of metals. The metal-containing semiconductor layer is formed overlying a substrate in a chamber. A precursor is introduced to deposit at least a portion of the metal-containing semiconductor layer. The precursor contains one or more elements that, if allowed to deposit in the metal-containing layer, would become impurity elements. A reactant gas is used to purify the metal-containing layer by removing impurity elements from the metal-containing layer which were introduced into the chamber by the precursor.
摘要翻译： 通过避免包含降低金属介电常数的污染元素的方法，形成具有高介电常数的含金属的半导体层。 含金属的半导体层形成在室内的基板上。 引入前体以沉积至少一部分含金属的半导体层。 前体含有一种或多种元素，如果允许沉积在含金属的层中，则会成为杂质元素。 反应气体用于通过从由前体引入室中的含金属层去除杂质元素来净化含金属层。
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公开(公告)号：US07297586B2
公开(公告)日：2007-11-20
申请号：US11043619
申请日：2005-01-26
IPC分类号： H01L21/8238
CPC分类号： H01L29/4966 , H01L21/28088 , H01L21/823842 , H01L21/823857 , H01L29/517
摘要： A CMOS device is provided which comprises (a) a substrate (103); (b) a gate dielectric layer (107) disposed on the substrate, the gate dielectric comprising a metal oxide; (c) an NMOS electrode (105) disposed on a first region of said gate dielectric; and (d) a PMOS electrode (115) disposed on a second region of said gate dielectric, the PMOS electrode comprising a conductive metal oxide; wherein the surface of said second region of said gate dielectric comprises a material selected from the group consisting of metal oxynitrides and metal silicon-oxynitrides.
摘要翻译： 提供一种CMOS器件，其包括（a）衬底（103）; （b）设置在所述衬底上的栅极电介质层（107），所述栅极电介质包括金属氧化物; （c）设置在所述栅极电介质的第一区域上的NMOS电极（105）; 和（d）设置在所述栅极电介质的第二区域上的PMOS电极（115），所述PMOS电极包括导电金属氧化物; 其中所述栅极电介质的所述第二区域的表面包括选自金属氧氮化物和金属硅氧氮化物的材料。
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10.发明授权公开(公告)号：US07132360B2
公开(公告)日：2006-11-07
申请号：US10865268
申请日：2004-06-10
IPC分类号： H01L21/4763 , H01L21/8344 , H01L21/8242 , H01L21/336
CPC分类号： H01L21/02181 , C23C16/0272 , H01L21/3141 , H01L21/31645
摘要： A method for treating a semiconductor surface to form a metal-containing layer includes providing a semiconductor substrate having an exposed surface. The exposed surface of the semiconductor substrate is treated by forming one or more metals overlying the semiconductor substrate but not completely covering the exposed surface of the semiconductor substrate. The one or more metals enhance nucleation for subsequent material growth. A metal-containing layer is formed on the exposed surface of the semiconductor substrate that has been treated. The treatment of the exposed surface of the semiconductor substrate assists the metal-containing layer to coalesce. In one embodiment, treatment of the exposed surface to enhance nucleation may be performed by spin-coating, atomic layer deposition (ALD), physical layer deposition (PVD), electroplating, or electroless plating. The one or more metals used to treat the exposed surface may include any rare earth or transition metal, such as, for example, hafnium, lanthanum, etc.
摘要翻译： 一种用于处理半导体表面以形成含金属层的方法包括提供具有暴露表面的半导体衬底。 半导体衬底的暴露表面通过形成覆盖半导体衬底但不完全覆盖半导体衬底的暴露表面的一种或多种金属来处理。 一种或多种金属增强成核以用于随后的材料生长。 在已经处理的半导体衬底的暴露表面上形成含金属层。 半导体衬底的暴露表面的处理有助于含金属层的聚结。 在一个实施方案中，可以通过旋涂，原子层沉积（ALD），物理层沉积（PVD），电镀或无电镀来进行暴露表面的处理以增强成核。 用于处理暴露表面的一种或多种金属可以包括任何稀土或过渡金属，例如铪，镧等。
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